- 您現在的位置：買賣IC網 > PDF目錄365828 > SMJ32020GBS 16-Bit Digital Signal Processor PDF資料下載
參數資料
| 型號： | SMJ32020GBS |
| 元件分類： | 數字信號處理 |
| 英文描述： | 16-Bit Digital Signal Processor |
| 中文描述： | 16位數字信號處理器 |
| 文件頁數： | 51/132頁 |
| 文件大?。?/td> | 1707K |
| 代理商： | SMJ32020GBS |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁當前第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁
SPRS145G
–
JULY 2000
–
REVISED FEBRUARY 2002
51
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
input qualifier circuitry
An input-qualifier circuitry qualifies the input signal to the CAP1
–
6, XINT1/2, ADCSOC and PDPINTA/B pins
in the 240xA devices. (The I/O functions of these pins do not use the input-qualifier circuitry). The state of the
internal input signal will change only after the pin is high/low for 6(12) clock edges. This ensures that a glitch
smaller than 5(11) CLKOUT cycles wide will not change the internal pin input state. The user must hold the pin
high/low for 6(12) cycles to ensure the device will see the level change. Bit 6 of the SCSR2 register controls
whether 6 clock edges (bit 6 = 0) or 12 clock edges (bit 6 = 1) are used to block 5- or 11-cycle glitches. On the
LC2402A, input qualification is for the CAP1, CAP2, CAP3, PDPINTA, and XINT2/ADCSOC pins.
enhanced analog-to-digital converter (ADC) module
A simplified functional block diagram of the ADC module is shown in Figure 11. The ADC module consists of
a 10-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module include:
10-bit ADC core with built-in S/H
16-channel, muxed inputs
Autosequencing capability provides up to 16
“
autoconversions
”
in a single session. Each conversion can
be programmed to select any 1 of 16 input channels
Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer
(i.e., two cascaded 8-state sequencers)
Sixteen result registers (individually addressable) to store conversion values
–
The digital value of the input analog voltage is derived by:
Digital Value
1023
Input Analog Voltage
V
REFHI
V
REFLO
V
REFLO
Multiple triggers as sources for the start-of-conversion (SOC) sequence
–
S/W
–
software immediate start
–
EVA
–
Event manager A (multiple event sources within EVA)
–
EVB
–
Event manager B (multiple event sources within EVB)
–
Ext
–
External pin (ADCSOC)
Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS
Sequencer can operate in
“
start/stop
”
mode, allowing multiple
“
time-sequenced triggers
”
to synchronize
conversions
EVA and EVB triggers can operate independently in dual-sequencer mode
Sample-and-hold (S/H) acquisition time window has separate prescale control
NOTE: The calibration and self-test features are not present in 240xA devices.
相關PDF資料 |
PDF描述 |
|---|---|
| TMP320LC2402APAGA | Transient Voltage Suppressor Diodes |
| TMP320LC2402APAGS | Transient Voltage Suppressor Diodes |
| TMP320LC2402APGA | Transient Voltage Suppressor Diodes |
| TM320C6201B | Transient Voltage Suppressor Diodes |
| TMS32020GBL | 16-Bit Digital Signal Processor |
相關代理商/技術參數 |
參數描述 |
|---|---|
| SMJ320C10-14FZM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
| SMJ320C10-14JDM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
| SMJ320C10-25FDM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
| SMJ320C10FDM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
| SMJ320C10FZM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Digital Signal Processor |
發(fā)布緊急采購，3分鐘左右您將得到回復。