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參數(shù)資料
| 型號(hào)： | SM5907 |
| 廠商： | Seiko NPC Corporation |
| 英文描述： | compression and non compression type shock-proof memory controller |
| 中文描述： | 壓縮和非壓縮式防震內(nèi)存控制器 |
| 文件頁(yè)數(shù)： | 9/30頁(yè) |
| 文件大小： | 231K |
| 代理商： | SM5907 |
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NIPPON PRECISION CIRCUITS-9
SM5906AF
Parameter
Symbol
Condition
Rating
Typ
1/96fs
1/48fs
Unit
Min
Max
ZSCK pulsewidth
ZSCK pulse cycle
ZSRDATA, ZLRCK, ZC2PO
output delay time
t
SCOW
t
SCOY
t
DHL
t
DLH
15 pF load
15 pF load
15 pF load
15 pF load
0
0
60
60
ns
ns
DRAM access timing (NRAS, NCAS, NWE, A0 to A10, D0 to D3)
Parameter
Symbol
Condition
Rating
Typ
4
Unit
Min
Max
NRAS pulsewidth
t
RASL
t
RASH
t
RCD
t
CASH
t
CASL
t
RADS
t
RADH
t
CADS
t
CADH
t
CWDS
t
CWDH
t
CRDS
t
CRDH
t
WEL
t
WCS
15 pF load
15 pF load
15 pF load
15 pF load
15 pF load
15 pF load
15 pF load
15 pF load
15 pF load
15 pF load
15 pF load
t
CY
(note)
t
CY
t
CY
t
CY
t
CY
t
CY
t
CY
t
CY
t
CY
t
CY
t
CY
ns
ns
t
CY
t
CY
ms
ms
ms
ms
ms
ms
2
NRAS falling edge to NCAS falling edge
NCAS pulsewidth
2
4
2
1
1
1
2
3
2
NRAS
Setup time
Hold time
Setup time
Hold time
Setup time
Hold time
Input setup
Input hold
falling edge to address
NCAS
falling edge to address
NCAS
falling edge to data write
NCAS
rising edge to data read
40
0
NWE pulsewidth
15 pF load
15 pF load
5
3
NWE falling edge to NCAS falling edge
Refresh cycle
(fs = 44.1 kHz playback)
4M
CD-DA MODE
3.0
2.6
1.3
5.9
5.2
2.6
DRAM
VCD MODE
t
REF
× 1
SVC MODE
Memory system ON
Read sequence operation
(RDEN=H)
16M
CD-DA MODE
DRAM
VCD MODE
× 1
SVC MODE
Note.
t
CY
is the system clock (CLK) input (384fs) cycle time.
t
CY
= 59 ns when fs = 44.1 kHz
ZSCK
ZSRDATA
ZLRCK
ZC2PO
0.5V
DD
t
DLH
0.5V
DD
DHL
t
SCOW
t
t
SCOW
t
SCOY
t
Serial output (ZSRDATA, ZLRCK, ZSCK ZC2PO pins)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SM5907AF | 制造商:NPC 制造商全稱:Nippon Precision Circuits Inc 功能描述:compression and non compression type shock-proof memory controller |
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| SM5921AF | 制造商:NPC 制造商全稱:Nippon Precision Circuits Inc 功能描述:8-channel Lip Sync Delay |
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