參數(shù)資料
型號: SM5907
廠商: Seiko NPC Corporation
英文描述: compression and non compression type shock-proof memory controller
中文描述: 壓縮和非壓縮式防震內(nèi)存控制器
文件頁數(shù): 22/30頁
文件大?。?/td> 231K
代理商: SM5907
NIPPON PRECISION CIRCUITS-22
SM5906AF
Correct data demodulation becomes impossible for
the CD signal processor IC when a disturbance
exceeding the RAM jitter margin occurs. The
YFLAG signal input pin is used to indicate when
such a condition has occurred.
The IC checks the YFLAG input and stops the write
sequence when such a disturbance has occurred,
and then makes FLAG6 active.
The YFLAG check method used changes depend-
ing on the YFLGS flag (85H command).
(see table1)
YFLAG, FLAG6
85H command
YFLGS
0
1
FLAG6 set conditions
FLAG6 reset conditions
0
1
When YFLAG = LOW
When YFLAG = HIGH
– By status read (90H command)
– When MSON = LOW or after system reset
Table 1. YFLAG signal check method
13.3ms
VWA(x)
VWA(x + 1)
YBLKCK
VWA
VWA latch set
WAQV set
Microcontroller data set
Refer to Microcontroller interface
Values shown are for rate fs. The values are 1/2 those shown at rate 2fs.
Fig 2. YBLKCK and VWA relationship
The VWA is determined according to the YBLKCK
pin and WAQV command. Refer to the timing chart
below.
1.YBLKCK is a 75 Hz clock(HIGH for 136
μ
s) when
used for normal read mode and it is a 150 Hz
clock when used for double-speed read mode,
synchronized to the CD format block end timing.
On the falling edge of this clock, stored compare-
connect write address WA1 is promoted to WA2
and stored.(see note 1).
2.The microcontroller checks the subcode and, if
confirmed to be correct, generates a WAQV com-
mand (80H).
3.When the WAQV command is received, the previ-
ously latched WA2 is stored as the VWA.
(Note 1) WA1, in VCD and SVC modes, is the
DRAM write address of the last sync data input
before the YBLKCK falling edge. In CDDA mode,
update occurs in the same manner so that WA1 is
updated every 588 data samples.
VWA (valid write address)
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