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參數(shù)資料
| 型號(hào)： | SM320C30HFGM50 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 數(shù)字信號(hào)處理器 |
| 文件頁數(shù)： | 1/47頁 |
| 文件大?。?/td> | 726K |
| 代理商： | SM320C30HFGM50 |
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SGUS014H FEBRUARY 1991 REVISED JUNE 2004
1
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
2
55
°
C to 125
°
C Operating Temperature
Range, QML Processing
Processed to MIL-PRF-38535 (QML)
Performance
SMJ320C30-40 (50-ns Cycle)
40 MFLOPS
20 MIPS
SMJ320C30-50 (40-ns Cycle)
50 MFLOPS
25 MIPS
Two 1K-Word
×
32-Bit Single-Cycle
Dual-Access On-Chip RAM Blocks
Validated Ada Compiler
64-Word
×
32-Bit Instruction Cache
32-Bit Instruction and Data Words,
24-Bit Addresses
40 / 32-Bit Floating-Point /Integer Multiplier
and Arithmetic Logic Unit (ALU)
Parallel ALU and Multiplier Execution in a
Single Cycle
On-Chip Direct Memory Access (DMA)
Controller for Concurrent I/O and CPU
Operation
Integer, Floating-Point, and Logical
Operations
One 4K-Word
×
32-Bit Single-Cycle
Dual-Access On-Chip ROM Block
description
Two 32-Bit External Ports
(24- and 13-Bit Address)
Two Serial Ports With Support for
8- / 16- /24- /32-Bit Transfers
Packaging
181-Pin Grid Array Ceramic Package
(GB Suffix)
196-Pin Ceramic Quad Flatpack With
Nonconductive Tie-Bar (HFG Suffix)
SMD Approval for 40- and 50-MHz Versions
Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
Zero-Overhead Loops With Single-Cycle
Branches
Interlocked Instructions for
Multiprocessing Support
32-Bit Barrel Shifter
Eight Extended-Precision Registers
(Accumulators)
Two- and Three-Operand Instructions
Conditional Calls and Returns
Block Repeat Capability
Fabricated Using Enhanced Performance
Implanted CMOS (EPIC ) by Texas
Instruments
Two 32-Bit Timers
The SMJ320C30 internal busing and special digital signal processor (DSP) instruction set has the speed and
flexibility to execute up to 50 MFLOPS. The SMJ320C30 device optimizes speed by implementing functions
in hardware that other processors implement through software or microcode. This hardware-intensive approach
provides performance previously unavailable on a single chip. The emphasis on total system cost has resulted
in a less expensive processor that can be designed into systems currently using costly bit-slice processors.
SMJ320C30-40: 50-ns single-cycle execution time, 5% supply
SMJ320C30-50: 40-ns single-cycle execution time, 5% supply
Copyright
2004, Texas Instruments Incorporated
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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EPIC is a trademark of Texas Instruments Incorporated.
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