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參數(shù)資料
| 型號： | SLUA110 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | PRACTICAL CONSIDERATIONS IN CURRENT MODE POWER SUPPLIES |
| 中文描述： | 實用的思考模式電源電流 |
| 文件頁數(shù)： | 7/19頁 |
| 文件大?。?/td> | 787K |
| 代理商： | SLUA110 |
APPLICATION NOTE
Not all PWM IC’s have a direct synchronization input/out-
put connection available to the internal oscillator In these
applications, the slave oscillator must be disabled and
driven in a different fashion. This approach may also be
required when using different PWMs amongst the slave
modules with different sync characteristics, or anti-phase
signals.
Unfortunately, there are several drawbacks to this method,
depending on the implementation. First, the PWM error
amplifier has no control over the pulse width in voltage
mode control. The error amplifier output is compared to a
digital signal instead of a sawtooth ramp, rendering its
attempts fruitless. The conventional soft start technique of
clamping the error amp output, thereby clamping the duty
cycle will not function. With no local timing ramp available,
the supply is completely under the direction of the sync
pulse source. Should the pulse become latched or
removed, the PWM outputs will either stay fully on, or fully
off, depending on the sync level input (voltage mode). Also,
without the local Ct ramp, the supply will not self-start,
remaining off until the sync stream appears. Slope com-
pensation for current mode controlled units requires addi-
tional components to generate the compensating ramp.
Every supply must be produced as a dedicated master, or
slave, and must be non-interchangeable with one another,
barring modification. This is only a brief list of the numerous
design drawbacks to this “open-ended” sync operation. To
circumvent these shortcomings, a universal sync circuit
has been developed with the following performance fea-
tures and benefits:
- Sync any PWM to/from any other PWM
- Sync any PWM to/from any number of other PWMs
- Sync from digital levels for simple system integration
- Bidirectional sync signal
- Any PWM can be master or slave with no modifications
- Each control circuit will start and run independently
of sync if sync signal is not present
- Localized ramp at Ct for slope compensation
- No critical frequency settings on each module
- High speed - minimum delays
- High noise immunity
- Low power requirements
- Remote off capability
- Minimal effect on frequency, duty cycle, and dead time
- Low cost and component count
- Small size
Sync Circuit Operating Principles
These optimal objectives can be obtained using a combi-
nation of both analog and digital signal inputs. The timing
capacitor Ct input will be used as a summing junction for
the analog sawtooth and digital sync input. The PWM is
allowed to run independently using its own Rt and Ct
components in standard configuration. When synchroni-
zation is required, a digital sync pulse will be super-
imposed on the Ct waveform.
U-111
When applied, the sync pulse quickly raises the voltage at
Ct above the PWM comparator upper threshold. This
forces a change in the oscillator charge/discharge status
and operation. The oscillator then begins its normal dis-
charge cycle synchronized to the sync signal. This digital
sync pulse simply adds to the analog Ct waveform, forcing
the Ct input voltage above the comparator upper
threshold.
Figure 16.
In practice, this approach is best implemented by bringing
Ct to ground through a small resistance, about 24 ohms.
This low value was selected to have minimal offset and
effects on the initial oscillator frequency. The sync pulse will
be applied across the 24 ohm resistor Since all PWMs
utilize the timing capacitor in their oscillator section, it is
both a convenient and universal node to work with.
Figure 17. Sync Circuit Implementation
Oscillator Timing Equations
The oscillator timing components must be first selected to
guarantee synchronization to the sync pulse. The sawtooth
amplitude must be lower than the upper threshold voltage
at the desired sync frequency. If not, the oscillator will run
in its normal mode and cross the upper threshold first,
before the sync pulse. This requirement dictates that the
PWM oscillator frequency must be lower than the sync
pulse frequency to trigger reliably. Typically, a ten percent
reduction in free running frequency can be accommo-
dated throughout the power supply. Adding the sync cir-
cuit will have minor effects on the PWM duty cycle, dead-
time and ramp amplitude. (These will be examined in
detail .)
3-112
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