參數(shù)資料
型號： SL28EB719AZIT
廠商： Silicon Laboratories Inc
文件頁數(shù)： 8/22頁
文件大小： 0K
描述： IC CLK CK505 TNLCK/TPCLF 48TSSOP
標(biāo)準(zhǔn)包裝： 2,000
系列： EProClock®
類型： 時(shí)鐘/頻率發(fā)生器，多路復(fù)用器
PLL： 是
主要目的： Intel CPU 服務(wù)器
輸入： 時(shí)鐘，晶體
輸出： HCSL，LVCMOS
電路數(shù)： 1
比率 - 輸入:輸出： 1:13
差分 - 輸入:輸出： 無/是
頻率 - 最大： 166.67MHz
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： *
封裝/外殼： *
供應(yīng)商設(shè)備封裝： *
包裝： *
SL28EB719
DOC#: SP-AP-0005 (Rev. AB)
Page 16 of 22
AC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
Crystal
TDC
XIN Duty Cycle
The device will operate reliably with input
duty cycles up to 30/70 but the REF clock
duty cycle will not be within specification
47.5
52.5
%
TPERIOD
XIN Period
When XIN is driven from an external
clock source
69.841
71.0
ns
TR/TF
XIN Rise and Fall Times
Measured between 0.3VDD and 0.7VDD
–10.0
ns
TCCJ
XIN Cycle to Cycle Jitter
As an average over 1-
s duration
–
500
ps
LACC
Long-term Accuracy
Measured at VDD/2 differential
–
250
ppm
LACC
Long-term Accuracy
Measured at VDD/2 differential
–
250
ppm
Clock Input
TDC
CLKIN Duty Cycle
Measured at VDD/2
47
53
%
TR/TF
CLKIN Rise and Fall Times
Measured between 0.2VDD and 0.8VDD
0.5
4.0
V/ns
TCCJ
CLKIN Cycle to Cycle Jitter
Measured at VDD/2
–
250
ps
TLTJ
CLKIN Long Term Jitter
Measured at VDD/2
–
350
ps
VIL
Input Low Voltage
XIN / CLKIN pin
–
0.8
V
VIH
Input High Voltage
XIN / CLKIN pin
2
VDD+0.3
V
IIL
Input LowCurrent
XIN / CLKIN pin, 0 < VIN <0.8
–
20
uA
IIH
Input HighCurrent
XIN / CLKIN pin, VIN = VDD
–
35
uA
CPU at 0.7V
TDC
CPU Duty Cycle
Measured at 0V differential
45
55
%
TPERIOD
83.33 MHz CPU Period
Measured at 0V differential at 0.1s
11.99880
12.00120
ns
TPERIODSS
83.33 MHz CPU Period, SSC
Measured at 0V differential at 0.1s
12.028872
12.03128
ns
TPERIODAbs
83.33 MHz CPU Absolute Period
Measured at 0V differential at 1clock
11.18969
12.16344
ns
TPERIODSSAbs 83.33 MHz CPU Absolute Period, SSC Measured at 0V differential at 1 clock
11.89687
12.16344
ns
TPERIOD
100 MHz CPU Period
Measured at 0V differential at 0.1s
9.99900
10.0010
ns
TPERIODSS
100 MHz CPU Period, SSC
Measured at 0V differential at 0.1s
10.02406
10.02607
ns
TPERIODAbs
100 MHz CPU Absolute Period
Measured at 0V differential at 1clock
9.87400
10.1260
ns
TPERIODSSAbs 100 MHz CPU Absolute Period, SSC
Measured at 0V differential at 1 clock
9.87406
10.1762
ns
TPERIOD
133 MHz CPU Period
Measured at 0V differential at 0.1s
7.49925
7.50075
ns
TPERIODSS
133 MHz CPU Period, SSC
Measured at 0V differential at 0.1s
7.51804
7.51955
ns
TPERIODAbs
133 MHz CPU Absolute period
Measured at 0V differential at 1 clock
7.41425
7.58575
ns
TPERIODSSAbs 133 MHz CPU Absolute period, SSC
Measured at 0V differential at1 clock
7.41430
7.62340
ns
TPERIOD
166 MHz CPU Period
Measured at 0V differential at 0.1s
5.99940
6.00060
ns
TPERIODSS
166 MHz CPU Period, SSC
Measured at 0V differential at 0.1s
6.01444
6.01564
ns
TPERIODAbs
166 MHz CPU Absolute period
Measured at 0V differential at 1 clock
5.91440
6.08560
ns
TPERIODSSAbs 166 MHz CPU Absolute period, SSC
Measured at 0V differential at 1 clock
5.91444
6.11572
ns
TCCJ
CPU Cycle to Cycle Jitter
Measured at 0V differential
–
85
ps
TCCJ (CPU2)
CPU Cycle to Cycle Jitter for CPU 2
Measured at 0V differential
–
125
ps
Skew
CPU0 to CPU1 skew
Measured at 0V differential
–
100
ps
LACC
Long-term Accuracy
Measured at 0V differential
–
100
ppm
TR / TF
CPU Rising/Falling Slew rate
Measured differentially from ±150 mV
2.5
8
V/ns
TRFM
Rise/Fall Matching
Measured single-endedly from ±75 mV
–
20
%
VHIGH
Voltage High
1.15
V
VLOW
Voltage Low
–0.3
–
V
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