參數(shù)資料
型號(hào): SL28647BLCT
廠(chǎng)商: Silicon Laboratories Inc
文件頁(yè)數(shù): 25/27頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK CK505 DIFF PAIR 72QFN
標(biāo)準(zhǔn)包裝: 2,000
類(lèi)型: 時(shí)鐘/頻率發(fā)生器,多路復(fù)用器
PLL:
主要目的: Intel CPU 服務(wù)器
輸入: 晶體
輸出: HCSL,LVCMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:22
差分 - 輸入:輸出: 無(wú)/是
頻率 - 最大: 400MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 85°C
安裝類(lèi)型: *
封裝/外殼: *
供應(yīng)商設(shè)備封裝: *
包裝: *
SL28647
.......................Document #: 001-05103 Rev *B Page 7 of 27
0
SRC0_STP_CTRL
Allow control of SRC0 with assertion of PCI_STP# or SW PCI_STP
0 = Free running, 1 = Stopped with PCI_STP#
Byte 5 Control Register 5
Bit
@Pup
Name
Description
7
0
LCD_96/100M_PD_Drive_Mode LCD_96/100 PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Tri-state
6
0
DOT96_PD_Drive_Mode
DOT96 PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Tri-state
5
0
RESERVED
4
0
RESERVED
3
0
PCIF0_STP_CTRL
Allow control of PCIF0 with assertion of SW and HW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
2
1
CPU2_STP_CTRL
Allow control of CPU[T/C]2 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
1
CPU1_STP_CTRL
Allow control of CPU[T/C]1 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
0
1
CPU0_STP_CTRL
Allow control of CPU[T/C]0 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Byte 4 Control Register 4 (continued)
Bit
@Pup
Name
Description
Byte 6 Control Register 6
Bit
@Pup
Name
Description
7
0
SRC_STP_Drive_Mode
SRC Stop Drive Mode
0 = Driven when PCI_STP# asserted
1 = Tri-state when PCI_STP# asserted
6
0
CPU2_STP_Drive_Mode
CPU2 Stop Drive Mode
0 = Driven when CPU_STP# asserted
1 = Tri-state when CPU_STP# asserted
5
0
CPU1_STP_Drive_Mode
CPU1 Stop Drive Mode
0 = Driven when CPU_STP# asserted
1 = Tri-state when CPU_STP# asserted
4
0
CPU0_STP_Drive_Mode
CPU0 Stop Drive Mode
0 = Driven when CPU_STP# asserted
1 = Tri-state when CPU_STP# asserted
3
0
SRC_[9:1]_PD_Drive_Mode SRC[9:1] PWRDWN Drive Mode
0 = Driven when PD asserted
1 = Tri-state when PD asserted
2
0
CPU2_PD_Drive_Mode
CPU2 PWRDWN Drive Mode
0 = Driven when PD asserted
1 = Tri-state when PD asserted
1
0
CPU1_PD_Drive_Mode
CPU1 PWRDWN Drive Mode
0 = Driven when PD asserted
1 = Tri-state when PD asserted
0
CPU0_PD_Drive_Mode
CPU0 PWRDWN Drive Mode
0 = Driven when PD asserted
1 = Tri-state when PD asserted
Byte 7 Control Register 7
Bit
@Pup
Name
Description
7
0
TEST_SEL
REF/N or Tri-state Select
0 = Tri-state, 1 = REF/N Clock
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