COUT Output Pin Capacitance 6" />
參數(shù)資料
型號: SL28610BLI
廠商: Silicon Laboratories Inc
文件頁數(shù): 8/23頁
文件大?。?/td> 0K
描述: IC CLK ATOM POULSBO PCIE 48QFN
標準包裝: 490
類型: 時鐘/頻率發(fā)生器,多路復(fù)用器
PLL:
主要目的: Intel CPU 服務(wù)器
輸入: 時鐘,晶體
輸出: HCSL,LVCMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:9
差分 - 輸入:輸出: 無/是
頻率 - 最大: 200MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: *
封裝/外殼: *
供應(yīng)商設(shè)備封裝: *
包裝: *
SL28610
...................... DOC #: SP-AP-0078 (Rev. 1.0) Page 16 of 23
COUT
Output Pin Capacitance
6
pF
LIN
Pin Inductance
7
nH
VXIH
Xin High Voltage
0.7VDD
VDD
V
VXIL
Xin Low Voltage
0
0.3VDD
V
Power
Power Consumption
100
mW
DC Electrical Specifications (continued)
Parameter
Description
Condition
Min.
Max.
Unit
AC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
Crystal
TDC
XIN Duty Cycle
The device operates reliably with input
duty cycles up to 30/70 but the REF clock
duty cycle will not be within specification
47.5
52.5
%
TPERIOD
XIN Period
When XIN is driven from an external
clock source
69.841
71.0
ns
TR/TF
XIN Rise and Fall Times
Measured between 0.3VDD and 0.7VDD
–10.0
ns
TCCJ
XIN Cycle to Cycle Jitter
As an average over 1-
s duration
500
ps
LACC
Long-term Accuracy
Measured at VDD/2 differential
250
ppm
Clock Input
TDC
CLKIN Duty Cycle
Measured at VDD/2
47
53
%
TR/TF
CLKIN Rise and Fall Times
Measured between 0.2VDD and 0.8VDD
0.5
4.0
V/ns
TCCJ
CLKIN Cycle to Cycle Jitter
Measured at VDD/2
250
ps
TLTJ
CLKIN Long Term Jitter
Measured at VDD/2
350
ps
VIL
Input Low Voltage
XIN / CLKIN pin
0.8
V
VIH
Input High Voltage
XIN / CLKIN pin
2
VDD+0.3
V
IIL
Input LowCurrent
XIN / CLKIN pin, 0 < VIN <0.8
20
uA
IIH
Input HighCurrent
XIN / CLKIN pin, VIN = VDD
35
uA
CPU at 0.7V
TDC
CPU Clock Duty Cycle
Measured at 0V differential at 0.1s
45
55
%
TPERIOD
100 MHz CPU Clock Period
Measured at 0V differential at 0.1s
9.997001
10.00300
ns
TPERIOD
133 MHz CPU Clock Period
Measured at 0V differential at 0.1s
7.497751
7.587251
ns
TPERIOD
166 MHz CPU Clock Period
Measured at 0V differential at 0.1s
5.998201
6.001801
ns
TPERIOD
200 MHz
CPU Clock Period
Measured at 0V differential at0.1s
4.99950
5.00050
ns
TPERIODSS
100 MHz CPU Clock Period, SSC
Measured at 0V differential at 0.1s
9.997001
10.05327
ns
TPERIODSS
133 MHz CPU Clock Period, SSC
Measured at 0V differential at 0.1s
7.412751
7.624950
ns
TPERIODSS
166 MHz CPU Clock Period, SSC
Measured at 0V differential at 0.1s
5.998201
6.031960
ns
TPERIODSS
200 MHz
CPU Clock Period, SSC
Measured at 0V differential at 0.1s
5.01203
5.01303
ns
TPERIODAbs
100 MHz CPU Clock Absolute period
Measured at 0V differential at 1 clock
9.912001
10.08800
ns
TPERIODAbs
133 MHz CPU Clock Absolute period
Measured at 0V differential at 1 clock
7.412751
7.587251
ns
TPERIODAbs
166 MHz CPU Clock Absolute period
Measured at 0V differential at1 clock
5.913201
6.086801
ns
TPERIODAbs
200 MHz
CPU Clock Absolute period
Measured at 0V differential at 1 clock
4.91450
5.08550
ns
TPERIODSSAbs 100 MHz CPU Clock Absolute period,
SSC
Measured at 0V differential at1 clock
9.912001
10.13827
ns
TPERIODSSAbs 133 MHz CPU Clock Absolute period,
SSC
Measured at 0V differential at 1 clock
7.412751
7.624950
ns
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