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參數(shù)資料
| 型號： | SL28610BLI |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 17/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK ATOM POULSBO PCIE 48QFN |
| 標(biāo)準(zhǔn)包裝： | 490 |
| 類型： | 時鐘/頻率發(fā)生器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務(wù)器 |
| 輸入： | 時鐘，晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:9 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 200MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
SL28610
........................ DOC #: SP-AP-0078 (Rev. 1.0) Page 3 of 23
Frequency Select Pin (FSB and FSC)
Apply the appropriate logic levels to FSB and FSC inputs
before CKPWRGD assertion to achieve host clock frequency
selection. When the clock chip sampled LOW on CKPWRGD
and indicates that VTT voltage is stable then FSB and FSC
input values are sampled. This process employs a one-shot
functionality and once the CKPWRGD sampled a valid LOW,
all other FSB, FSC, and CKPWRGD transitions are ignored
except in test mode.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting at power-up. The use of this interface is
optional. Clock device register changes are normally made at
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in Table 2.
The block write and block read protocol is outlined in Table 3
while Table 4 outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h).
.
40
VSS
GND
Ground
41
VDD1.5_IO
PWR
1.5V Power Supply for differential output
42
VDD1.5_CORE
PWR
1.5V Power Supply for core
43
CPU1#
O, DIF Complementary Host Differential clock
44
CPU1
O, DIF True Host Differential clock
45
VSS_CPU
GND
Ground
46
VDD1.5_IO
PWR
1.5V Power Supply for differential output
47
CPU2#
O, DIF Complementary Host Differential clock
48
CPU2
O, DIF True Host Differential clock
Table 1. Frequency Select Pin (FSB and FSC)
FSC
FSB
CPU
PCIe
LCD
DOT96
REF
1
0
100 MHz
96 MHz
14.318 MHz
0
133 MHz
100 MHz
96 MHz
14.318 MHz
0
1
166 MHz
100 MHz
96 MHz
14.318 MHz
1
200 MHz
100 MHz
96 MHz
14.318 MHz
Pin Definitions (continued)
Pin No.
Name
Type
Description
Table 2. Command Code Definition
Bit
Description
7
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0)
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Bit
Description
Bit
Description
1Start
1
Start
8:2
Slave address–7 bits
8:2
Slave address–7 bits
9
Write
9
Write
10
Acknowledge from slave
10
Acknowledge from slave
18:11
Command Code–8 bits
18:11
Command Code–8 bits
19
Acknowledge from slave
19
Acknowledge from slave
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SL28610BLIT | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 AtomPoulsbo Handheld Embed.1.5V PCIe G1 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SL28610BLITR | 制造商:Silicon Laboratories Inc 功能描述: |
| SL28647BLC | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Montevina RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SL28647BLCT | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Montevina RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SL28647CLC | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Montevina RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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