參數(shù)資料
型號: SL28506BZI-2T
廠商: Silicon Laboratories Inc
文件頁數(shù): 21/27頁
文件大?。?/td> 0K
描述: IC CLOCK CK505 PCIE GEN2 56TSSOP
標準包裝: 2,000
類型: 時鐘/頻率發(fā)生器
PLL:
主要目的: Intel CPU 服務(wù)器
輸入: 時鐘,晶體
輸出: HCSL,LVCMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:19
差分 - 輸入:輸出: 無/是
頻率 - 最大: 400MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 56-TSSOP
包裝: 帶卷 (TR)
SL28506-2
.........................DOC #: SP-AP-0021 (Rev AB) Page 3 of 27
26
VDD_SRC_IO
PWR
IO power supply for SRC outputs.
27
SRC4
O, DIF 100MHz Differential serial reference clocks.
28
SRC4#
O, DIF 100MHz Differential serial reference clocks.
29
SRC5#CPU_STP#
I/O,
Dif
3.3V tolerant input for stopping CPU outputs/100MHz Differential serial reference
clocks.
30
SRC5/PCI_STP#
I/O,
Dif
3.3V tolerant input for stopping PCI and SRC outputs/100MHz Differential serial
reference clocks.
31
VDD_SRC
PWR
3.3V Power supply for SRC PLL.
32
SRC6#
O, DIF 100MHz Differential serial reference clocks.
33
SRC6
O, DIF 100MHz Differential serial reference clocks.
34
VSS_SRC
GND
Ground for outputs.
35
SRC7#/OE#_6
I/O,
Dif
100MHz Differential serial reference clocks/3.3V OE#6 Input controlling SRC6.
(Default SRC7, 100MHz clock).
36
SRC7/OE#_8
I/O,
Dif
100MHz Differential serial reference clocks/3.3V OE#8 Input controlling SRC8.
(Default SRC7, 100MHz clock).
37
VDD_SRC_IO
PWR
0.7V power supply for SRC outputs.
38
SRC8#/CPU2#_ITP#
O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 at CKPWRGD
assertion = SRC8
ITP_EN = 1 @ CKPWRGD assertion = CPU2
(Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11
Bit3:2)
39
SRC8/CPU2_ITP
O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 at CKPWRGD
assertion = SRC8
ITP_EN = 1 @ CKPWRGD assertion = CPU2
(Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte 11
Bit3:2)
40
IO_VOUT
PWR
Integrated Linear Regulator Control.
41
VDD_CPU_IO
PWR
IO Power supply for CPU outputs.
42
CPU1#
O, DIF Differential CPU clock outputs. (Note: CPU1 is an iAMT clock in iAMT mode depending
on the configuration set in Byte 11 Bit3:2)
43
CPU1
O, DIF Differential CPU clock outputs. (Note: CPU1 is an iAMT clock in iAMT mode depending
on the configuration set in Byte 11 Bit3:2)
44
VSS_CPU
GND
Ground for outputs.
45
CPU#0
O, DIF Differential CPU clock outputs.
46
CPU0
O, DIF Differential CPU clock outputs.
47
VDD_CPU
PWR
3.3V Power supply for CPU PLL.
48
CKPWRGD/PD#
I
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,
FS_B, FS_C, FS_D, SRC5_SEL, and ITP_EN.
After CKPWRGD (active HIGH) assertion, this pin becomes a real-time input for
asserting power down (active LOW).
49
FSB/TEST_MODE
I
3.3V tolerant input for CPU frequency selection.
Selects Ref/N or Tri-state when in test mode
0 = Tri-state, 1 = Ref/N.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
50
VSS_REF
GND
Ground for outputs.
51
XOUT
O, SE 14.318MHz Crystal output. (Float XOUT if using CLKIN)
52
XIN/CLKIN
I
14.318MHz Crystal input or 3.3V, 14.318MHz input clock signal.
53
VDD_REF
PWR
3.3V Power supply for outputs and also maintains SMBUS registers during
power-down.
56 TSSOP Pin Definition (continued)
Pin No.
Name
Type
Description
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