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參數(shù)資料
| 型號： | SL16020DCT |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 100 MHz, OTHER CLOCK GENERATOR, PDSO10 |
| 封裝： | 3 X 3 MM, 0.75 MM HEIGHT, HALOGEN FREE AND ROHS COMPLIANT, TDFN-10 |
| 文件頁數(shù)： | 7/10頁 |
| 文件大?。?/td> | 132K |
| 代理商： | SL16020DCT |
Rev 2.2, August 1, 2010
Page 6 of 10
SL16020DC
External Resistor Dividers for 3-Level Logic Implementation
3-Level Logic
HIGH=VDD
VDD
5K
Ω
SSEL0
or
SSEL1
INPUT
7/3
3-Level Logic
LOW=VSS
VSS
5K
Ω
SSEL0
or
SSEL1
INPUT
7/3
HIGH (H) = VDD
MIDDLE (M) = VDD/2
LOW (L) = VSS
3-Level Logic
Middle=VDD/2
VSS
VDD
5K
Ω
5K
Ω
SSEL0
or
SSEL1
INPUT
7/3
Figure 3. FSEL0 and FSEL1 Spread % Selection Logic
Note: SSEL0 and SSEL1 pins use 3-Level L(LOW) = VSS, M(MIDDLE)=VDD/2 and H(HIGH) = VDD
3-Level logic to provide 9 spread % values at SSCLK (pin 5) as given in Table 5.
Use 5k
Ω/5kΩ external resistor dividers at SSEL0 and SSEL1 pins from VDD to VSS to obtain VDD/2
for M=VDD/2 Logic level as shown above in Figure 3.
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