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參數(shù)資料
| 型號(hào)： | SL16020DCT |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 100 MHz, OTHER CLOCK GENERATOR, PDSO10 |
| 封裝： | 3 X 3 MM, 0.75 MM HEIGHT, HALOGEN FREE AND ROHS COMPLIANT, TDFN-10 |
| 文件頁(yè)數(shù)： | 5/10頁(yè) |
| 文件大小： | 132K |
| 代理商： | SL16020DCT |
Rev 2.2, August 1, 2010
Page 4 of 10
SL16020DC
Table 4. AC Electrical Characteristics (C-Grade)
Unless otherwise stated VDD= 3.3V+/-10%, CL=15pF and Ambient Temperature range -10 to +85 Deg C
Parameter
Symbol
Condition
Min
Typ
Max
Unit
Frequency Range
FR-1
Input crystal or clock range, +/-10 ppm
accuracy if a crystal is used
-
27.000
-
MHz
Frequency Range
FR-2
REFCLK, Pin 9
-
27.000
-
MHz
Frequency Range
FR-3
SSCLK, Pin 5
-
100.000
-
MHz
Frequency Accuracy
FACC1
REFCLK, Pin 9
-
+/-0
-
ppm
Frequency Accuracy
FACC2
SSCLK, Pin 5, SSEL0/1=0
-
+/-0
-
ppm
Rise and Fall Time
TR/F-1
REFCLK, Pin 9, CL=5pF, measured
from 20% to 80% of VDD
-
1.0
1.5
ns
Rise and Fall Time
TR/F-2
REFCLK, Pin 9, CL=15pF, measured
from 20% to 80% of VDD
-
1.5
2.0
ns
Rise and Fall Time
TR/F-3
SSCLK, Pin 5, CL=5pF, measured
from 20% to 80% of VDD
-
0.75
1.0
ns
Rise and Fall Time
TR/F-4
SSCLK, Pin 5, CL=15pF, measured
from 20% to 80% of VDD
-
1.5
1.75
ns
Output Duty Cycle
DC
SSCLK and REFCLK , Pins 5 and 9
measured at VDD/2, CL=15pF
45
50
55
%
Cycle-to-Cycle Jitter
CCJ1
SSCLK, Pin 5, all S0/1 states
-100
+/-50
100
ps
Cycle-to-Cycle Jitter
CCJ2
REFCLK, Pins 9, all S0/1 states
-150
+/-100
150
ps
Long Term Jitter
LTJ
REFCLK, Pins 9, 10,000 cycles, all
S0/1 states
-
150
250
ps
Power-up Time
(VDD)
tPU1
Time from 0.9VDD to valid frequency
at output Pins 5 and 9
-
2.0
5.0
ms
Spread Percent
Change Settling Time
tSS%
Time from SSEL0/1 change to stable
SSCLK with spread %
-
1.0
ms
Modulation Frequency
MF
SSCLK, 100MHz nominal, Pin 5
31
32
33
kHz
Modulation Type and
Slew Rate
FMTSR
SSCLK, Pin 5, Triangular Modulation
Profile
-
0.125
%/μs
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