- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄9058 > SL15100ZIT (Silicon Laboratories Inc)IC CLOCK SSCG 1PLL 2CH 8TSSOP PDF資料下載
參數(shù)資料
| 型號(hào)： | SL15100ZIT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 5/16頁(yè) |
| 文件大小： | 0K |
| 描述： | IC CLOCK SSCG 1PLL 2CH 8TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | EProClock® |
| 類型： | * |
| PLL： | 帶旁路 |
| 輸入： | 時(shí)鐘，晶體 |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 頻率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/無(wú) |
| 電源電壓： | 2.25 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)當(dāng)前第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)
Rev 1.8, August 10, 2007
Page 13 of 16
SL15100
External Components & Design Considerations
Typical Application Schematic
SL15100
XIN(3)
VDD(1)
XOUT(2)
PD#(4)
SSCLK(7)
SSON#(8)
+/-1.5% Spread
66MHz
27MHz
0.1
μF
VDD
VSS(5)
REFCLK(6)
No Spread
27MHz
VDD
Comments and Recommendations
Decoupling Capacitor:
A decoupling capacitor of 0.1μF must be used between VDD and VSS on the pins 1 and 5.
Place the capacitor on the component side of the PCB as close to the VDD pin as possible. The PCB trace to the
VDD pin and to the GND via should be kept as short as possible Do not use vias between the decoupling capacitor
and the VDD pin.
Series Termination Resistor: A series termination resistor is recommended if the distance between the output
(SSCLK) and the load is over 1 inch. The nomi
nal impedance of the SSCLK output is about 30 Ω. Use 20 Ω
resistor in series with the output to terminate 50Ω trace impedance and place 20 Ω resistor as close to the SSCLK
output as possible.
Crystal and Crystal Load: Use only parallel resonant fundamental crystals. DO NOT USE higher overtone crystals.
To meet the crystal initial accuracy specification (in ppm); the internal on-chip programmable capacitors PCin and
PCout must be programmed to match the crystal load requirement. These values are given by the formula below:
PCin(pF) =PCout(pF)= [(CL(pF) – Cp(pF)/2)] x 2
Where CL is crystal load capacitor as given by the crystal datasheet and Cp(pF) is the compensation factor for the
total parasitic capacitance at XIN or XOUT pin including PCB related parasitic capacitance.
As an example; if a crystal with CL=18pF is used and Cp=4pF, by using the above formula, PCin=PCout=[(18-(4/2)] x
2 = 32pF. Programming PCin and PCout to 32pF assures that this crystal sees an equivalent load of 18pF and no
other external crystal load capacitor is needed. Deviating from the crystal load specification could cause an increase
in frequency accuracy in ppm. Refer to the Table 5 for the recommended crystal specifications.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MK2308G-1HLFTR | IC PLL ZD BUFFER HS 16-TSSOP |
| ICS674R-01LFT | IC DIVIDER USER CONFIG 28-SSOP |
| ICS525R-11LFT | IC PECL CLK USER CONFIG 28-SSOP |
| DS1844S-100 | IC POT DIG QUAD 100K 20-SOIC |
| DS18030-050 | IC POT DUAL ADDRESS 50K 16-DIP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SL15100ZIT-XXX | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Prigrammable Spread Spectrum Clock Generator (SSCG) |
| SL15100ZI-XXX | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Prigrammable Spread Spectrum Clock Generator (SSCG) |
| SL15101 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Programmable Spread Spectrum Clock Generator (SSCG) |
| SL15101ZCT-XXX | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Programmable Spread Spectrum Clock Generator (SSCG) |
| SL15101ZC-XXX | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Programmable Spread Spectrum Clock Generator (SSCG) |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。