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參數(shù)資料
| 型號： | SK10EL11WDT |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 10EL SERIES, LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封裝： | 0.150 INCH, SOIC-8 |
| 文件頁數(shù)： | 5/6頁 |
| 文件大?。?/td> | 119K |
| 代理商： | SK10EL11WDT |
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www.semtech.com
HIGH-PERFORMANCE PRODUCTS
SK10/100EL11W
Revision 4/July 18, 2002
Notes:
1.
10EL circuits are designed to meet the DC specifications shown in the table after thermal
equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit
board and transverse airflow greater than 500 lfpm is maintained. Outputs are terminated through
a 50
resistor to VCC -2.0V except where otherwise specified on the individual data sheets.
2.
100K circuits are designed to meet the DC specifications shown in the table where transverse
airflow greater than 500 lfpm is maintained.
3.
Within-device skew defined as identical transitions on similar paths through a device.
4.
Duty cycle skew is the difference between a TPLH and TPHL propagation delay through a device.
5.
Minimum input swing for which AC parameters guaranteed.
6.
CMR range is referenced to the most positive side of the differential input signal. Normal operation is
obtained if the high level falls within the specified range and the peak-to-peak voltage lies between
VPP(min) and 1V. The lower end of the CMR range varies 1:1 with VEE and is equal to VEE + 1.6V.
7.
For standard ECL DC specifications, refer to the ECL Logic Family Standard DC Specifications Data
Sheet.
8.
For part ordering descriptions, see HPP Part Ordering Information Data Sheet.
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AC Characteristics (continued)
Ordering Information
AN1003 - Termination Techniques for ECL / LVECL / PECL / LVPECL Devices
AN1004 - Interfacing Between LVDS and ECL / LVECL / PECL / LVPECL
AN1005 - Using ECL / LVECL Devices as PECL / LVPECL
AN1006 - Designing with 10K and 100K ECL / PECL Devices
Application Notes
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SK10EL15WD | 10EL SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| SK100EL15WU | 100EL SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), UUC |
| SK100EL15WD | 100EL SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| SK10EL31WD | 10EL SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8 |
| SK10EL31WDT | 10EL SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SK10EL11WMS | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:1:2 Differential Fanout Buffer |
| SK10EL11WMST | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:1:2 Differential Fanout Buffer |
| SK10EL11WU | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:1:2 Differential Fanout Buffer |
| SK10EL12W | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:Low Impedance Driver |
| SK10EL12WD | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:Low Impedance Driver |
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