參數(shù)資料
型號(hào): SK10EL31WD
元件分類: 鎖存器
英文描述: 10EL SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8
封裝: SOIC-8
文件頁數(shù): 1/5頁
文件大小: 81K
代理商: SK10EL31WD
HIGH-PERFORMANCE PRODUCTS
1
www.semtech.com
Revision 2/January 28, 2002
SK10/100EL31W
D Flip - Flop with Set and Reset
Description
Features
Functional Block Diagram
The SK10/100EL31W is a D Flip-Flop with Set and
Reset. The device is fully compatible with the MC10/
100EL31 and MC10/100LVEL31 devices, but operates
from a –5.5V to –3.3V supply. With propagation delays
and output transition times significantly faster than
the E131, SK10/100EL31W is ideally suited for those
applications which require the ultimate in AC
perfor mance.
Both set and reset inputs are
asynchronous, level triggered signals. Data enters the
master portion of the flip-flop when clock is LOW, is
transferred to the slave and thus the outputs, upon a
positive transition of the clock.
Extended Supply Voltage Range: (VEE = –5.5V to
–3.0V, VCC = 0V) or (VCC = +3.0V to +5.5V, VEE =
0V)
350 ps typical Propagation Delay
2.9 GHz Toggle Frequency
Fully Compatible with MC10/100EL31
and MC10/100LVEL31
75K
W Internal Input Pulldown Resistors
Specified Over Industrial Temperature Range:
–40oC to 85oC
ESD Protection of >4000V
Small Outline SOIC Package
Flammability Rate: UL-94 code V-0.
Moisture Sensitivity: Level 1.
1
2
3
4
8
7
6
5
S
R
D
CLK
VCC
VEE
Q
Q*
Flip Flop
D
S
R
PinDescription
n
i
Pn
o
i
t
c
n
u
F
*
Q
,
Q
S
D
K
L
C
R
s
t
u
p
t
u
O
a
t
a
D
t
e
S
t
u
p
n
I
a
t
a
D
t
u
p
n
I
k
c
o
l
C
t
e
s
e
R
DS
R
K
L
CQ
L
H
X
L
H
L
H
L
H
Z
X
L
H
L
f
e
d
n
U
Truth Table
Z = LOW to HIGH Transition
相關(guān)PDF資料
PDF描述
SK10EL31WDT 10EL SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8
SK10EL32WU 10EL SERIES, PRESCALER, UUC
SK10EL33WDT 10EL SERIES, PRESCALER, PDSO8
SK10EL34WD 10EL SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
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