參數(shù)資料
型號(hào): SK100LVE111PJT
元件分類: 時(shí)鐘及定時(shí)
英文描述: 100LVE SERIES, LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28
封裝: PLASTIC, LCC-28
文件頁(yè)數(shù): 5/6頁(yè)
文件大小: 414K
代理商: SK100LVE111PJT
5
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TEST AND MEASUREMENT PRODUCTS
Revision 3 / January 29, 2003
SK100LVE111
Notes:
1. 100LVE111 circuits are designed to meet the DC specifications shown in the table where transverse
airflow greater than 500 lfpm is maintained.
2. These values are for VCC = 3.3V. Level Specifications will vary 1:1 with VCC.
3. The differential propagation delay is defined as the delay from the crossing points of the differential
input signals to the crossing point of the differential output signals.
4. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to
the 50% point of the output signal.
5. The within-device skew is defined as the worst case difference between any two similar delay paths
within a single device.
6. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the
propagation delay. The VPP(min) is AC limited for the LVE111 as a differential input as low as 500 mV
will still produce full ECL levels at the output.
7.
CMR range is referenced to the most positive side of the differential input signal. Normal operation is
obtained if the high level falls within the specified range and the peak-to-peak voltage lies between
VPP(min) and 1V. The lower end of the CMR range varies 1:1 with VEE and is equal to VEE + 1.5V.
8.
For part ordering description, see TMD Part Ordering Information Data Sheet.
AC Characteristics (Continued)
AN1002 - Interfacing Between ECL / LVECL / PECL / LVPECL - to - TTL / LVTTL / CMOS / LVCMOS
AN1003 - Termination Techniques for ECL / LVECL / PECL / LVPECL Devices
AN1004 - Interfacing Between LVDS and ECL / LVECL / PECL / LVPECL
AN1005 - Using ECL / LVECL Devices as PECL / LVPECL
AN1006 - Designing with 10K and 100K ECL / PECL Devices
Application Notes
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