參數(shù)資料
型號(hào)： SJ80C32XXX-12SV
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 12 MHz, MICROCONTROLLER, CQCC44
封裝： JLCC-44
文件頁數(shù)： 44/109頁
文件大小： 10824K
代理商： SJ80C32XXX-12SV
288
7593L–AVR–09/12
AT90USB64/128
24.7
USB reset
The USB controller sends a USB Reset when the firmware set the RESET bit. The RSTI bit is
set by hardware when the USB Reset has been sent. This triggers an interrupt if the RSTE has
been set.
When a USB Reset has been sent, all the Pipe configuration and the memory allocation are
reset. The General Host interrupt enable register is left unchanged.
If the bus was previously in suspend mode (SOFEN = 0), the USB controller automatically
switches to the resume mode (HWUPI is set) and the SOFEN bit is set by hardware in order to
generate SOF immediately after the USB Reset.
24.8
Address setup
Once the Device has answer to the first Host requests with the default address (0), the Host
assigns a new address to the device. The Host controller has to send a USB reset to the device
and perform a SET ADDRESS control request, with the new address to be used by the Device.
This control request ended, the firmware write the new address into the UHADDR register. All
following requests, on every Pipes, will be performed using this new address.
When the Host controller send a USB reset, the UHADDR register is reset by hardware and the
following Host requests will be performed using the default address (0).
24.9
Remote wake-up detection
The Host Controller enters in Suspend mode when clearing the SOFEN bit. No more Start Of
Frame is sent on the USB bus and the USB Device enters in Suspend mode 3ms later.
The Device awakes the Host Controller by sending an Upstream Resume (Remote Wake-Up
feature). The Host Controller detects a non-idle state on the USB bus and set the HWUPI bit. If
the non-Idle correspond to an Upstream Resume (K state), the RXRSMI bit is set by hardware.
The firmware has to generate a downstream resume within 1ms and for at least 20ms by setting
the RESUME bit.
Once the downstream Resume has been generated, the SOFEN bit is automatically set by hard-
ware in order to generate SOF immediately after the USB resume.
24.10 USB pipe reset
The firmware can reset a Pipe using the pipe reset register. The configuration of the pipe and
the data toggle remains unchanged. Only the bank management and the status bits are reset to
their initial values.
To completely reset a Pipe, the firmware has to disable and then enable the pipe.
24.11 Pipe data access
In order to read or to write into the Pipe Fifo, the CPU selects the Pipe number with the UPNUM
register and performs read or write action on the UPDATX register.
Host
Ready
Host
Suspend
SOFE=1
or HWUP=1
SOFE=0
相關(guān)PDF資料
PDF描述
S80C52EXXX-20SHXXX:D 8-BIT, MROM, 20 MHz, MICROCONTROLLER, PQCC44
SCC9521002-01C 8-BIT, 30 MHz, MICROCONTROLLER, CDIP40
S80C52XXX-12D 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44
S80C32E-40SHXXX:RD 8-BIT, 40 MHz, MICROCONTROLLER, PQCC44
S80C52TXXX-12 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44
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