參數(shù)資料
型號(hào)： SJ80C32XXX-12SV
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 12 MHz, MICROCONTROLLER, CQCC44
封裝： JLCC-44
文件頁(yè)數(shù)： 108/109頁(yè)
文件大小： 10824K
代理商： SJ80C32XXX-12SV
810
32117D–AVR-01/12
AT32UC3C
set and bit i of the TXORCH field in the Status Register is set, where i is the current transmit
channel number. If the TXSAME bit in the Mode Register is zero, then a zero data word is trans-
mitted in case of underrun. If MR.TXSAME is one, then the previous data word for the current
transmit channel number is transmitted.
Data words are right-justified in the RHR and THR registers. For 16-bit compact stereo, the left
sample uses bits 15 through 0 and the right sample uses bits 31 through 16 of the same data
word. For 8-bit compact stereo, the left sample uses bits 7 through 0 and the right sample uses
bits 15 through 8 of the same data word.
30.6.9
DMA Operation
The Receiver and the Transmitter can each be connected either to one single Peripheral DMA
channel or to one Peripheral DMA channel per data channel. This is selected by writing to the
MR.RXDMA and MR.TXDMA bits. If a single Peripheral DMA channel is selected, all data sam-
ples use IISC Receiver or Transmitter DMA channel 0.
The Peripheral DMA reads from the RHR register and writes to the RHR register for all audio
channels, successively.
The Peripheral DMA transfers may use 32-bit word, 16-bit halfword, or 8-bit byte according to
the value of the MR.DATALENGTH field.
30.6.10
Loop-back Mode
For debugging purposes, the IISC can be configured to loop back the Transmitter to the
Receiver. Writing a one to the MR.LOOP bit will internally connect ISDO to ISDI, so that the
transmitted data is also received. Writing a zero to MR.LOOP will restore the normal behavior
with independent Receiver and Transmitter. As for other changes to the Receiver or Transmitter
configuration, the IISC Receiver and Transmitter must be disabled before writing to the MR reg-
ister to update MR.LOOP.
30.6.11
Interrupts
An IISC interrupt request can be triggered whenever one or several of the following bits are set
in the Status Register (SR): Receive Ready (RXRDY), Receive Overrun (RXOR), Transmit
Ready (TXRDY), or Transmit Underrun (TXOR).
The interrupt request will be generated if the corresponding bit in the Interrupt Mask Register
(IMR) is set. Bits in IMR are set by writing a one to the corresponding bit in the Interrupt Enable
Register (IER), and cleared by writing a one to the corresponding bit in the Interrupt Disable
Register (IDR). The interrupt request remains active until the corresponding bit in SR is cleared
by writing a one the corresponding bit in the Status Clear Register (SCR).
For debugging purposes, interrupt requests can be simulated by writing a one to the correspond-
ing bit in the Status Set Register (SSR).
相關(guān)PDF資料
PDF描述
S80C52EXXX-20SHXXX:D 8-BIT, MROM, 20 MHz, MICROCONTROLLER, PQCC44
SCC9521002-01C 8-BIT, 30 MHz, MICROCONTROLLER, CDIP40
S80C52XXX-12D 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44
S80C32E-40SHXXX:RD 8-BIT, 40 MHz, MICROCONTROLLER, PQCC44
S80C52TXXX-12 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SJ81200 制造商:Rochester Electronics LLC 功能描述:- Bulk
SJ83100 制造商:ON Semiconductor 功能描述:SJ83100 - Trays 制造商:Rochester Electronics LLC 功能描述:- Bulk
SJ83180 制造商:ON Semiconductor 功能描述:NPN TO-3 METAL PWR TRANSISTOR - Trays 制造商:Rochester Electronics LLC 功能描述:NPN TO-3 METAL PWR TRANSISTOR - Bulk
SJ84140 制造商:Rochester Electronics LLC 功能描述:- Bulk
SJ-870 制造商:NEL 制造商全稱:Nel Frequency Controls,inc 功能描述:CRYSTAL CLOCK OSCILLATORS
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*