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參數(shù)資料
| 型號： | SiI3726CBHU |
| 廠商： | Silicon Image, Inc. |
| 英文描述： | SATA Port Multiplier |
| 中文描述： | SATA端口倍增器 |
| 文件頁數(shù)： | 13/41頁 |
| 文件大?。?/td> | 375K |
| 代理商： | SII3726CBHU |
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SiI3726 SATA Port Multiplier
Data Sheet
Addr
0x02
GSCR[02]
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0121-C1
13
Name
Port
Information
31
30
29
28
27
26
25
24
RSVD0
23
22
21
20
19
18
17
16
RSVD0
15
14
13
12
11
10
9
8
RSVD0
7
6
5
4
3
2
1
0
RSVD0
Number of Fan-out ports
Bit
Label
R/W
Description
Default
This register defines port information associated with the SiI3726
.
31:4
RSVD0
R
This bit field is reserved and returns a zero value.
0x0000
000
0x6
3:0
Number of
Fan-out
ports
R
This bit field is set to 0x06 to indicate that SiI3726 supports one host and
five device ports.
Addr
0x20
GSCR[32]
Name
Error
Information
31
30
29
28
27
26
25
24
RSVDRW
20
RSVDRW
12
RSVDRW
4
Error
Informat
ion
Description
23
22
21
19
18
17
16
15
14
13
11
10
9
8
7
RSVDRW
6
5
3
2
1
0
Error
Informat
ion
Error
Informat
ion
Error
Informat
ion
Error
Informat
ion
Error
Informat
ion
Default
0x0000
0b0
Bit
31:06
5
Label
RSVDRW
Error
Information
Error
Information
Error
Information
Error
Information
Error
Information
Error
Information
R/W
R/W
R/W
This bit field is reserved and returns the value written to it.
This bit is set to 1 when the bits in port5 PSCR[1] SError register are set.
The bits used for this bit are selected by the GSCR[33]..
This bit is set to 1 when the bits in port4 PSCR[1] SError register are set.
The bits used for this bit are selected by the GSCR[33].
This bit is set to 1 when the bits in port3 PSCR[1] SError register are set.
The bits used for this bit are selected by the GSCR[33].
This bit is set to 1 when the bits in port2 PSCR[1] SError register are set.
The bits used for this bit are selected by the GSCR[33].
This bit is set to 1 when the bits in port1 PSCR[1] SError register are set.
The bits used for this bit are selected by the GSCR[33].
This bit is set to 1 when the bits in port0 PSCR[1] SError register are set.
The bits used for this bit are selected by the GSCR[33].
4
R/W
0b0
3
R/W
0b0
2
R/W
0b0
1
R/W
0b0
0
R/W
0b0
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