參數(shù)資料
型號(hào)： SiI3114CT176
廠商： Silicon Image, Inc.
英文描述： PCI to Serial ATA Controller
中文描述： PCI到Serial ATA控制器
文件頁數(shù)： 52/127頁
文件大?。?/td> 598K
代理商： SII3114CT176
SiI
3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
Internal Register Space – Base Address 4
SiI
-DS-0103-D
44
2007 Silicon Image, Inc.
Access to these registers is modified by the “shadow” Device Select bits.
These registers are 32-bits wide and define the internal operation of the
SiI
3114. The access types are defined as
follows: R=read, W=write, and C=clearable by some write operation. Access to this register is through the PCI I/O
space. Table 21 shows the internal register space for base 4 addresses.
Table 21.
SiI
3114 Internal Register Space – Base Address 4
Register Name
Address
Offset
31 16
15 00
Access
Type
00
H
Reserved
PCI Bus Master
Status –
Channel 0/2
PRD Table Address – Channel 0/2
PCI Bus Master
Status –
Channel 1/3
PRD Table Address – Channel 1/3
Software Data
PCI Bus Master
Command –
Channel 0/2
R/W
04
H
R/W
08
H
Reserved
Reserved
PCI Bus Master
Command –
Channel 1/3
R/W
0C
H
R/W
PCI Bus Master – Channel 0/2
Address Offset: 00
H
Access Type: Read/Write
Reset Value: 0x0000_XX00
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
P
P
P
R
C
P
P
W
C
Software
Reserved
P
R
P
This register defines the PCI bus master register for Channel 0/2 in the
SiI
3114. See “PCI Bus Master – Channel
X
” section on page 53 for bit definitions. The value in the “shadow” Channel 0/2 Device Select bit is used to
control access to the appropriate Channel 0 (Master; bit is 0) or Channel 2 (Slave; bit is 1) PCI Bus Master
register bits. (The “shadow” Channel 1/3 Device Select bit controls the Channel 1/3 DMA Comp bit.)
PRD Table Address – Channel 0/2
Address Offset: 04
H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PRD Table Address – Channel 0/2
R
This register defines the PRD Table Address register for Channel 0/2 in the
SiI
3114. The register bits are also
mapped to PCI Configuration Space, Offset 74
H
and Base Address 5, Offset 04
H
. See “PRD Table Address –
Channel
X
” section on page 54 for bit definitions. Writing to this register address results in both the Channel 0 and
Channel 2 PRD Table Address registers being written. The read value is selected based upon the “shadow”
Channel 0/2 Device Select bit.
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SII3114CTU 制造商:Silicon Image Inc 功能描述:PCI to Serial ATA Controller 176-Pin TQFP 制造商:SILICON 功能描述:
SII3124A 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI-X to Serial ATA Controller
SII3124ACBHU 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI-X to Serial ATA Controller
SII3132 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI Express to 2-Port Serial ATA II Host Controller
SII3132CNU 制造商:Silicon Image Inc 功能描述:PCI Express to Serial ATA Controller 88-Pin QFN
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