參數(shù)資料
型號： SiI3114CT176
廠商： Silicon Image, Inc.
英文描述： PCI to Serial ATA Controller
中文描述： PCI到Serial ATA控制器
文件頁數(shù)： 50/127頁
文件大?。?/td> 598K
代理商： SII3114CT176
SiI
3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
Internal Register Space – Base Address 2
SiI
-DS-0103-D
42
2007 Silicon Image, Inc.
Access to these registers is modified by the “shadow” Channel 1/3 Device Select bit. The “shadow” Channel 1/3
Device Select bit is written from bit 4 of the byte written to the Channel 1/3 Task File Device+Head register (offset
06
H
).
These registers are 32-bits wide and define the internal operation of the
SiI
3114. The access types are defined as
follows: R=read, W=write, and C=clearable by some write operation. Access to this register is through the PCI I/O
space. Table 19 shows the internal register space for base 2 addresses.
Table 19.
SiI
3114 Internal Register Space – Base Address 2
Register Name
Address
Offset
31
Starting Sector
Number
Command+Status
16
15
00
Features (W)
Error (R)
Cylinder High
Access
Type
00
H
Sector Count
Data
R/W
04
H
Device+Head
Cylinder Low
R/W
Channel 1/3 Task File Register 0
Address Offset: 00
H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Starting Sector Number
Sector Count
Features (W) Error (R)
Data (byte access)
Data (word access)
Data (dword access)
This register defines four of the Channel 1/3 Task File registers in the
SiI
3114. The register bits are also mapped
to Base Address 5, Offset C0
H
. See “Channel
X
Task File Register 0” section on page 62 for bit definitions. The
value in the “shadow” Channel 1/3 Device Select bit is used to select the Task File registers for either Channel 1
(Master; bit is 0) or Channel 3 (Slave; bit is 1).
Channel 1/3 Task File Register 1
Address Offset: 04
H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Command + Status
Device+Head
Cylinder High
Cylinder Low
This register defines four of the Channel 1/3 Task File registers in the
SiI
3114. The register bits are also mapped
to Base Address 5, Offset C4
H
. See “Channel
X
Task File Register 1” section on page 62 for bit definitions. Except
for writing the Device+Head Task File register, the value in the “shadow” Channel 1/3 Device Select bit is used to
select the Task File registers for either Channel 1 (Master; bit is 0) or Channel 3 (Slave; bit is 1). For writing the
Device+Head Task File register, the value being written to bit 4 of the register (the Device Select bit) is used to
select the Task File register for either Channel 1 (Master; bit is 0) or Channel 3 (Slave; bit is 1); a 0 is always
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SII3114CTU 制造商:Silicon Image Inc 功能描述:PCI to Serial ATA Controller 176-Pin TQFP 制造商:SILICON 功能描述:
SII3124A 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI-X to Serial ATA Controller
SII3124ACBHU 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI-X to Serial ATA Controller
SII3132 制造商:SILICONIMAGE 制造商全稱:SILICONIMAGE 功能描述:PCI Express to 2-Port Serial ATA II Host Controller
SII3132CNU 制造商:Silicon Image Inc 功能描述:PCI Express to Serial ATA Controller 88-Pin QFN
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