參數(shù)資料
型號(hào)： SII1151
廠商： Silicon Image, Inc.
英文描述： TELECOMMANDER USB(PC&Mac OS X) FOR DESKTOP ROVER
中文描述： PanelLink接收機(jī)
文件頁(yè)數(shù)： 37/44頁(yè)
文件大?。?/td> 377K
代理商： SII1151
SiI
1151
PanelLink Receiver
Data Sheet
Adjusting Equalizer and Bandwidth
The
SiI
1151 provides access to several internal registers that can be set to optimize the connection to a variety
of source devices and accommodate a range of cable lengths.
33
SiI
-DS-0023-C
The
SiI
1151 provides access to several internal registers that can be set to optimize the connection to a variety
of source devices and accommodate a range of cable lengths. Pins must be set in Programmable Mode
according to the details shown in Table 17 on page 31. The rules for setting the registers for best operation are
flexible; the only goal is to achieve best visual performance on the display. In general these guidelines apply.
The EQ_DATA bits correspond to the cable length, with 0000 applying to the longest cables, and 1111
applying to the shortest cables. Cable quality and DVI signal source quality also factor into this setting,
so there is no exact correspondence of settings to cable length. With good cable quality and a fully DVI-
compliant source, cable lengths in excess of 20m are achievable at SXGA.
The LBW bits correspond to the clock recovery PLL bandwidth. DVI-compliant transmitters are best
accommodated by a setting of 4MHz as dictated by the DVI 1.0 spec. Recovery of data from non DVI-
compliant transmitters is often better when the bandwidth is set to a higher value. Refer to Table 19 for
setting information.
Programmable Mode I
2
C Registers
The internal registers are used as shown in Table 18. The I
2
C Device Address for
SiI
1151 is 0x76.
The registers are set to their default values when the PD# pin is driven LOW (as well as when the MODE
pin is set to HIGH). If the design does not provide a means of explicitly controlling the PD# signal, an RC
circuit should be attached to the PD# pin to ensure that the I2C logic is reset properly at powerup. Refer
to “Programmable Mode Reset Recommendations” on Page 31 for information.
Table 18. Internal I
2
C Registers
Addr.
0x0
0x1
0x2
0x3
0x4
0x5-0x8
0x9
0xA
0xB
0xC-0xF
Notes
1. All values are Bit 7 [msb] and Bit 0 [lsb].
2. RW (or unmarked) indicates a read/write field. RO indicates a read-only field.
3. RSVD registers must not be accessed. RSVD bits or fields should be written as 0 when writing other bits in the
register.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VND_IDL (RO)
VND_IDH (RO)
DEV_IDL (RO)
DEV_IDH (RO)
DEV_REV (RO)
RSVD
RSVD
STAG_OUT#
RSVD
EQ_DATA[3:0]
ST
RSVD
RSVD
OCK_INV
CKST
RSVD
RSVD
ZONEO (RO)
RSVD
LBW[1:0]
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