
SiI
1151
PanelLink Receiver
Data Sheet
SiI
-DS-0023-C
12
Calculating Setup and Hold Times
Output setup and hold times between video output clock (ODCK) and video data (including HSYNC, VSYNC and
DE) are functions of the worst case duty cycle specification for ODCK and the worst case clock to output delay.
For the
SiI
1151 output pins, only the minimum output setup and hold times are critical.
The
SiI
1151 provides the OCK_INV feature, described on page 22, to allow external logic to decode data with
either a rising or falling clock edge.
OCK_INV=0 Case
For OCK_INV=0, the worst-case setup time occurs when the clock to output delay is at a maximum (latest data)
and the ODCK duty cycle is at a minimum (earliest falling edge). Conversely, the worst case hold time occurs
when the clock to output delay is at a minimum (earliest next data) and the ODCK duty cycle is at a maximum
(latest falling edge). This is shown in Figure 5. The falling active ODCK edge is shown with an arrowhead.
Figure 5. Receiver Output Setup and Hold Times – OCK_INV=0
Note:
For Staggered Output timing in 2Pix/clk mode, refer to Figure 15.
Actual setup and hold times can be derived from the clock period at the operating frequency of interest. Clock
duty cycle must also be taken into account when calculating setup and hold times.
Setup Time
to ODCK: T
ODCK
*T
DUTY
{min} - T
CK2OUT
{max}
Hold Time
from ODCK: T
ODCK
* (1 - T
DUTY
{max}) + T
CK2OUT
{min}
T
DUTY
= min
T
= max
External clock
ODCK
with
OCK_INV=0
Q
DE
VSYNC
HSYNC
50%
T
HD
T
SU
T
= min
T
DUTY
= max
50%
Rising edge used
internally to clock
out Data (Q), DE,
VSYNC, HSYNC
T
DLY
-
inverter delays
External logic uses
this falling clock edge
to sample data
Internal
Clock