參數(shù)資料
型號: Si9182
廠商: Vishay Intertechnology,Inc.
英文描述: Micropower 250-mA CMOS LDO Regulator With Error Flag/Power-On-Reset(250mA微功耗CMOS低壓差穩(wěn)壓器(帶電源錯誤標(biāo)記和加電復(fù)位))
中文描述: 微250毫安的CMOS LDO穩(wěn)壓器在錯誤旗/上電復(fù)位(250mA的微功耗的CMOS低壓差穩(wěn)壓器(帶電源錯誤標(biāo)記和加電復(fù)位))
文件頁數(shù): 1/10頁
文件大?。?/td> 115K
代理商: SI9182
Si9182
Vishay Siliconix
New Product
Document Number: 71150
S-01484—Rev. B, 03-Jul-00
www.vishay.com FaxBack 408-970-5600
1
Micropower 250-mA CMOS LDO Regulator
With Error Flag/Power-On-Reset
Low 105-mV Dropout at 250-mA Load
Guaranteed 250-mA Output Current
500-mA Peak Output Current Capability
Uses Low ESR Ceramic Output Capacitor
Fast Load and Line Transient Response
Only 100- V(rms) Noise With Noise Bypass
Capacitor
1- A Maximum Shutdown Current
Built-in Short Circuit and Thermal Protection
Out-Of-Regulation Error Flag (Power Good or POR)
Fixed 1.5-V, 1.8-V, 2.0-V, 2.5-V, 2.8-V, 3.0-V, 3.3-V,
5.0-V, or Adjustable Output Voltage Options
Other Output Voltages Available by Special Order
Cellular Phones
Laptop and Palm Computers
PDA, Digital Still Cameras
The Si9182 is a 250-mA CMOS LDO (low dropout) voltage
regulator. The device features ultra low ground current and
dropout voltage to prolong battery life in portable electronics.
The Si9182 offers line/load transient response and ripple
rejection superior to that of bipolar or BiCMOS LDO regulators.
The device is designed to maintain regulation while delivering
500-mA peak current. This is useful for systems that have high
surge current upon turn-on. The Si9182 is designed to drive
the lower cost ceramic, as well as tantalum, output capacitors.
The device is guaranteed stable from maximum load current
down to 0-mA load. In addition, an external noise bypass
capacitor connected to the device’s C
NOISE
pin will lower the
LDO’s output noise for low noise applications.
The Si9182 also includes an out-of-regulation error flag. When
the output voltage is 5% below its nominal output voltage, the
error flag output goes low. If a capacitor is connected to the
device’s delay pin, the error flag output pin will generate a
delayed power-on-reset signal.
FIGURE 1.
Fixed Output
FIGURE 2.
Adjustable Output
FIGURE 3.
Low Noise, Full Features Application
C
NOISE
SD
1
8
DELAY
ERROR
2
7
GND
SENSE/ADJ
3
6
V
IN
V
OUT
4
5
GND
V
IN
2.2 F
2.2 F
V
OUT
Si9182
C
NOISE
1
8
DELAY
ERROR
2
7
GND
SENSE/ADJ
3
6
V
IN
V
OUT
4
5
GND
V
IN
2.2 F
2.2 F
V
OUT
Si9182
C
NOISE
1
8
DELAY
ERROR
2
7
GND
SENSE/ADJ
3
6
V
IN
V
OUT
4
5
GND
V
IN
2.2 F
2.2 F
V
OUT
Si9182
POR
ON/OFF
0.1 F
0.1 F
1 M
SD
SD
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