參數(shù)資料
型號： Si786
廠商： Vishay Intertechnology,Inc.
英文描述： Dual-Output Power-Supply Controller(用于便攜電腦電源轉(zhuǎn)換的雙輸出步降轉(zhuǎn)換器)
中文描述： 雙輸出電源控制器（用于便攜電腦電源轉(zhuǎn)換的雙輸出步降轉(zhuǎn)換器）
文件頁數(shù)： 13/13頁
文件大?。?/td> 497K
代理商： SI786
Si786
Vishay Siliconix
FaxBack 408-970-5600, request 70189
www.siliconix.com
S-60752—Rev. G, 05-Apr-99
13
DESIGN CONSIDERATIONS
Inductor Design
Three specifications are required for inductor design:
inductance (L), peak inductor current (I
LPEAK
), and coil
resistance (R
L
). The equation for computing inductance is:
Where:
V
OUT
V
IN(MAX)
f
I
OUT
LIR
= Output voltage (3.3 V or 5 V);
= Maximum input voltage (V);
= Switching frequency, normally 300 kHz;
= Maximum dc load current (A);
= Ratio of inductor peak-to-peak ac current to
average dc load current, typically 0.3.
When LIR is higher, smaller inductance values are
acceptable, at the expense of increased ripple and higher
losses.
The peak inductor current (I
LPEAK
) is equal to the steady-state
load current (I
OUT
) plus one half of the peak-to-peak ac
current (I
LPP
). Typically, a designer will select the ac inductor
current to be 30% of the steady-state current, which gives
I
LPEAK
equal to 1.15 times I
OUT
.
The equation for computing peak inductor current is:
OUTPUT CAPACITORS
The output capacitors determine loop stability and ripple
voltage at the output. In order to maintain stability, minimum
capacitance and maximum ESR requirements must be met
according to the following equations:
and,
Where:
C
F
V
REF
V
OUT
R
CS
GBWP = Gain-bandwidth product, 60 kHz;
ESR
CF
= Output filter capacitor ESR (
).
= Output filter capacitance (F)
= Reference voltage, 3.3 V;
= Output voltage, 3.3 V or 5 V;
= Sense resistor (
);
Both minimum capacitance and maximum ESR requirements
must be met. In order to get the low ESR, a capacitance value
of two to three times greater than the required minimum may
be necessary.
The equation for output ripple in continuous current mode is:
The equations for capacitive and resistive components of the
ripple in pulse-skipping mode are:
The total ripple, V
OUT(RPL)
, can be approximated as follows:
if
V
OUT(RPL)
(R) < 0.5 V
OUT(RPL)
(C),
then
V
OUT(RPL)
= V
OUT(RPL)
(C),
otherwise, V
OUT(RPL)
= 0.5 V
OUT(RPL)
(C) + V
OUT(RPL)
(R)
Lower Voltage Input
The application circuit shown here can be easily modified to
work with 5.5-V to 12-V input voltages. Oscillation frequency
should be set at 200 kHz and increase the output capacitance
to 660 μF on the 5-V output to maintain stable performance up
to 2 A of load current. Operation on the 3.3-V supply will not
be affected by this reduced input voltage.
L
V
IN MAX
V
OUT
V
–
)
)
)
-------------------------------------------------------------------
=
I
LPEAK
I
OUT
V
--------------------------------------------------------------------
V
IN MAX
V
–
)
)
+
=
C
F
V
2
V
OUT
(
)
R
CS
(
GBWP
(
)
-----------------------------------------------------------------------------
>
ESR
CF
V
-----------------------------------
(
R
REF
)
<
V
OUT RPL
)
I
LPP MAX
)
ESR
CF
F
)
----------------------------------------
+
×
=
V
OUT RPL
)
C
( )
4
R
CS
(
---------------------------------
4
–
)
C
F
(
)
OUT
-------------
IN
OUT
---------–
+
×
=
V
OUT RPL
)
R
( )
0.02
-----------------------------------------
(
ESR
CS
)
=
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