參數(shù)資料
型號(hào): SI5369D-C-GQ
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 26/84頁(yè)
文件大小: 0K
描述: IC CLK MULT JITTER ATTEN 100TQFP
標(biāo)準(zhǔn)包裝: 90
系列: DSPLL®
類型: *
PLL:
輸入: LVCMOS
輸出: CML,CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 4:5
差分 - 輸入:輸出: 是/是
頻率 - 最大: 243MHz
除法器/乘法器: 是/是
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-TQFP
供應(yīng)商設(shè)備封裝: 100-TQFP(14x14)
包裝: 托盤(pán)
Si5369
32
Rev. 1.0
Reset value = 0000 0000
Register 8.
Bit
D7
D6D5D4
D3D2D1
D0
Name
HLOG_4[1:0]
HLOG_3[1:0]
HLOG_2[1:0]
HLOG_1[1:0]
Type
R/W
Bit
Name
Function
7:6
HLOG_4 [1:0] HLOG_4 [1:0].
00: Normal operation
01: Holds CKOUT4 output at static logic 0. Entrance and exit from this state will occur
without glitches or runt pulses.
10: Holds CKOUT4 output at static logic 1. Entrance and exit from this state will occur
without glitches or runt pulses.
11: Reserved
5:4
HLOG_3 [1:0] HLOG_3 [1:0].
00: Normal operation
01: Holds CKOUT3 output at static logic 0. Entrance and exit from this state will occur
without glitches or runt pulses.
10: Holds CKOUT3 output at static logic 1. Entrance and exit from this state will occur
without glitches or runt pulses.
11: Reserved.
3:2
HLOG_2 [1:0] HLOG_2 [1:0].
00: Normal operation
01: Holds CKOUT2 output at static logic 0. Entrance and exit from this state will occur
without glitches or runt pulses.
10: Holds CKOUT2 output at static logic 1. Entrance and exit from this state will occur
without glitches or runt pulses.
11: Reserved.
1:0
HLOG_1 [1:0] HLOG_1 [1:0].
00: Normal operation
01: Holds CKOUT1 output at static logic 0. Entrance and exit from this state will occur
without glitches or runt pulses.
10: Holds CKOUT1 output at static logic 1. Entrance and exit from this state will occur
without glitches or runt pulses.
11: Reserved
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