- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄8973 > SI5367C-C-GQ (Silicon Laboratories Inc)IC CLOCK MULTIPLIER PROG 100TQFP PDF資料下載
參數(shù)資料
| 型號： | SI5367C-C-GQ |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 9/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK MULTIPLIER PROG 100TQFP |
| 標準包裝： | 90 |
| 系列： | DSPLL® |
| 類型： | 時鐘乘法器 |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | CML，CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 4:5 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 346MHz |
| 除法器/乘法器： | 無/是 |
| 電源電壓： | 1.71 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP |
| 供應商設備封裝： | 100-TQFP（14x14） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁當前第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁
Si5367
Rev. 0.5
17
3. Functional Description
The Si5367 is a low jitter, precision clock multiplier for
applications requiring clock multiplication without jitter
attenuation. The Si5367 accepts four clock inputs
ranging from 10 to 707 MHz and generates five
frequency-multiplied clock outputs ranging from 2 kHz
to 945 MHz and select frequencies to 1.4 GHz. The
device provides virtually any frequency translation
combination across this operating range. Independent
dividers are available for every input clock and output
clock, so the Si5367 can accept input clocks at different
frequencies and it can generate output clocks at
different frequencies. The Si5367 input clock frequency
and clock multiplication ratio are programmable through
an I2C or SPI interface. Silicon Laboratories offers a
PC-based software utility, DSPLLsim, that can be used
to determine the optimum PLL divider settings for a
given
input
frequency/clock
multiplication
ratio
combination that minimizes phase noise and power
consumption. This utility can be downloaded from
http://www.silabs.com/timing (click on Documentation).
The Si5367 is based on Silicon Laboratories' 3rd-
generation DSPLL technology, which provides any-
frequency synthesis in a highly integrated PLL solution
that eliminates the need for external VCXO and loop
filter components. The Si5367 PLL loop bandwidth is
digitally programmable and supports a range from
150kHz to 1.3MHz. The DSPLLsim software utility can
be used to calculate valid loop bandwidth settings for a
given input clock frequency/clock multiplication ratio.
The Si5367 monitors all input clocks for loss-of-signal
and provides a LOS alarm when it detects missing
pulses on its inputs.
In the case when the input clocks enter alarm
conditions, the PLL will freeze the DCO output
frequency near its last value to maintain operation with
an internal state close to the last valid operating state.
The Si5367 has five differential clock outputs. The
signal format of the clock outputs is programmable to
support LVPECL, LVDS, CML, or CMOS loads. If not
required, unused clock outputs can be powered down to
minimize power consumption. In addition, the phase of
each output clock may be adjusted in relation to the
other output clocks. The resolution varies from 800 ps to
2.2 ns depending on the PLL divider settings. Consult
the DSPLLsim configuration software to determine the
phase offset resolution for a given input clock/clock
multiplication
ratio
combination.
For
system-level
debugging, a bypass mode is available which drives the
output clock directly from the input clock, bypassing the
internal DSPLL. The device is powered by a single 1.8
or 2.5 V supply.
3.1. Further Documentation
Consult
the
Silicon
Laboratories
Any-Frequency
Precision Clock Family Reference Manual (FRM) for
detailed information about the Si5367. Additional design
support is available from Silicon Laboratories through
your distributor.
Silicon
Laboratories
has
developed
a
PC-based
software utility called DSPLLsim to simplify device
configuration, including frequency planning and loop
bandwidth selection. The FRM and this utility can be
downloaded from http://www.silabs.com/timing; click on
Documentation.
相關PDF資料 |
PDF描述 |
|---|---|
| MS3452L36-15S | CONN RCPT 35POS BOX MNT W/SCKT |
| VE-B61-MV-F3 | CONVERTER MOD DC/DC 12V 150W |
| VE-B61-MV-F2 | CONVERTER MOD DC/DC 12V 150W |
| AD5732RBREZ | IC DAC DUAL 14BIT SERIAL 24TSSOP |
| GTC00R-22-19S | CONN RCPT 14POS WALL MNT W/SCKT |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SI5367C-C-GQR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 mP-Program Precision Clk Multiplier 4/5 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5367-EVB | 制造商:Silicon Laboratories Inc 功能描述: |
| SI5368 | 制造商:SILABS 制造商全稱:SILABS 功能描述:ANY-RATE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR |
| Si5368A-B-GQ | 功能描述:鎖相環(huán) - PLL ANY-RATE CLK MULT JITTER ATTEN 5 OUTS RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| SI5368A-B-GQR | 制造商:Silicon Laboratories Inc 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。