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參數(shù)資料
| 型號： | SI5365-C-GQR |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 5/28頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK MULTIPLIER PROG 100TQFP |
| 標準包裝： | 250 |
| 系列： | DSPLL® |
| 類型： | 時鐘乘法器 |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | CML，CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 4:5 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.05GHz |
| 除法器/乘法器： | 無/是 |
| 電源電壓： | 1.71 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP |
| 供應商設備封裝： | 100-TQFP（14x14） |
| 包裝： | 帶卷 (TR) |
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Si5365
Rev. 0.5
13
3. Functional Description
The Si5365 is a low jitter, precision clock multiplier for
high-speed communication systems, including SONET
OC-48/OC-192, SDH STM-16/STM-64, Ethernet, and
Fibre Channel, in which the application requires clock
multiplication without jitter attenuation. The Si5365
accepts four clock inputs ranging from 19.44 to
707 MHz and generates five frequency-multiplied clock
outputs ranging from 19.44 to 1050 MHz. By default the
four clock inputs are at the same frequency and the five
clock outputs are at the same frequency. Two of the
output clocks can be divided down further to generate
an integer sub-multiple frequency. The input clock
frequency and clock multiplication ratio are selectable
from a table of popular SONET, Ethernet, and Fibre
Channel frequencies. In addition to providing clock
multiplication in SONET and datacom applications, the
Si5365
supports
SONET-to-datacom
frequency
translations. Silicon Laboratories offers a PC-based
software utility, DSPLLsim, that can be used to look up
valid Si5365 frequency translations. This utility can be
downloaded from http://www.silabs.com/timing (click on
Documentation).
The Si5365 is based on Silicon Laboratories' 3rd-
generation DSPLL technology, which provides any-
frequency synthesis in a highly integrated PLL solution
that eliminates the need for external VCXO and loop
filter components. The Si5365 PLL loop bandwidth is
digitally programmable via the BWSEL[1:0] pins and
supports a range from 150 kHz to 1.3 MHz. The
DSPLLsim software utility can be used to calculate valid
loop bandwidth settings for a given input clock
frequency/clock multiplication ratio.
The Si5365 monitors all input clocks for loss-of-signal
and provides a LOS alarm when it detects a missing
clock.
In the case when the input clocks enter alarm
conditions, the PLL will freeze the DCO output
frequency near its last value to maintain operation with
an internal state close to the last valid operating state.
The Si5365 has five differential clock outputs. The
signal format of the clock outputs is programmable to
support LVPECL, LVDS, CML, or CMOS loads. If not
required, unused clock outputs can be powered down to
minimize
power
consumption.
For
system-level
debugging, a bypass mode is available which drives the
output clock directly from the input clock, bypassing the
internal DSPLL. The device is powered by a single 1.8,
2.5, or 3.3 V supply.
3.1. Further Documentation
Consult
the
Silicon
Laboratories
Any-Frequency
Precision Clock Family Reference Manual (FRM) for
detailed information about the Si5365. Additional design
support is available from Silicon Laboratories through
your distributor.
Silicon
Laboratories
has
developed
a
PC-based
software utility called DSPLLsim to simplify device
configuration, including frequency planning and loop
bandwidth selection. The FRM and this utility can be
downloaded from http://www.silabs.com/timing; click on
Documentation.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5365-EVB | 制造商:Silicon Laboratories Inc 功能描述: |
| SI5366 | 制造商:SILABS 制造商全稱:SILABS 功能描述:PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR |
| Si5366-B-GQ | 功能描述:鎖相環(huán) - PLL PIN-PROGRAM CLK MULT /JITTER ATTEN 5 OUT RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| SI5366-B-GQR | 制造商:Silicon Laboratories Inc 功能描述: |
| Si5366-C-GQ | 功能描述:鎖相環(huán) - PLL PIN-PROGRAM CLK MULT /JITTER ATTEN 5 OUT RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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