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參數(shù)資料
| 型號： | SI5365-C-GQR |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 11/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK MULTIPLIER PROG 100TQFP |
| 標準包裝： | 250 |
| 系列： | DSPLL® |
| 類型： | 時鐘乘法器 |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | CML，CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 4:5 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.05GHz |
| 除法器/乘法器： | 無/是 |
| 電源電壓： | 1.71 V ~ 2.75 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP |
| 供應商設備封裝： | 100-TQFP（14x14） |
| 包裝： | 帶卷 (TR) |
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Si5365
Rev. 0.5
19
80
95
SFOUT1
SFOUT0
I
3-Level
Signal Format Select.
Three level inputs that select the output signal format (common mode
voltage and differential swing) for all of the clock outputs except
CKOUT5 (see DBL5).
Bypass mode is not available with CMOS outputs. When VDD = 3.3 V,
for thermal reasons, there are restrictions on the number of LVPECL
and CMOS outputs. See the Si53xx-RM reference manual for details.
These pins have both weak pullups and weak pulldowns and default to
M.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
82
83
CKOUT1–
CKOUT1+
OMULTI
Clock Output 1.
Differential output clock with a frequency specified by FRQSEL and
FRQTBL. Output signal format is selected by SFOUT pins. Output is
differential for LVPECL, LVDS, and CML compatible modes. For CMOS
format, both output pins drive identical single-ended clock outputs.
85
DBL34
I
LVCMOS
Output 3 and 4 Disable.
Active high input. When active, entire CKOUT3 and CKOUT4 divider
and output buffer path is powered down. CKOUT3 and CKOUT4 out-
puts will be in tristate mode during powerdown.
This pin has a weak pullup.
87
88
CKOUT5–
CKOUT5+
OMULTI
Clock Output 5.
Fifth high-speed clock output with a frequency specified by FRQSEL
and FRQTBL. Output signal format is selected by SFOUT pins. Output
is differential for LVPECL, LVDS, and CML compatible modes. For
CMOS format, both output pins drive identical single-ended clock out-
puts.
92
93
CKOUT2+
CKOUT2–
OMULTI
Clock Output 2.
Differential output clock with a frequency specified by FRQSEL and
FRQTBL. Output signal format is selected by SFOUT pins. Output is
differential for LVPECL, LVDS, and CML compatible modes. For CMOS
format, both output pins drive identical single-ended clock outputs.
Table 6. Si5365 Pin Descriptions (Continued)
Pin #
Pin Name
I/O Signal Level
Description
SFOUT[1:0]
Signal Format
HH
Reserved
HM
LVDS
HL
CML
MH
LVPECL
MM
Reserved
ML
LVDS—Low Swing
LH
CMOS
LM
Disable
LL
Reserved
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SI5365-EVB | 制造商:Silicon Laboratories Inc 功能描述: |
| SI5366 | 制造商:SILABS 制造商全稱:SILABS 功能描述:PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR |
| Si5366-B-GQ | 功能描述:鎖相環(huán) - PLL PIN-PROGRAM CLK MULT /JITTER ATTEN 5 OUT RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| SI5366-B-GQR | 制造商:Silicon Laboratories Inc 功能描述: |
| Si5366-C-GQ | 功能描述:鎖相環(huán) - PLL PIN-PROGRAM CLK MULT /JITTER ATTEN 5 OUT RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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