PUPDATE Pin control2,3 MultiSynth output <18" />
參數(shù)資料
型號: SI5338P-A-GM
廠商: Silicon Laboratories Inc
文件頁數(shù): 42/44頁
文件大?。?/td> 0K
描述: IC CLK GEN I2C BUS PROG 24QFN
標(biāo)準(zhǔn)包裝: 490
系列: MultiSynth™
類型: *
PLL:
輸入: CML,HCSL,HSCL,LVDS,LVPECL,晶體
輸出: CMOS,HCSL. HSTL. LVDS. LVPECL. SSTL
電路數(shù): 1
比率 - 輸入:輸出: 2:4
差分 - 輸入:輸出: 是/是
頻率 - 最大: 350MHz
除法器/乘法器: 是/是
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 24-QFN(4x4)
包裝: 托盤
Si5338
Rev. 1.3
7
Phase Increment/Decrement
Update Time
PUPDATE
Pin control2,3
MultiSynth output <18 MHz
Number of periods of
MultiSynth output frequency
—10
12
Periods
Frequency Increment/
Decrement Step Size
fSTEP
R divider not used
1
See
Note 2
ppm
MultiSynth range for frequency
increment/decrement
fRANGE
R divider not used
5
Fvco/8
MHz
Frequency Increment/
Decrement Update Time
fUPDATE
Pin control2,3
MultiSynth output >18 MHz
——
667
ns
Frequency Increment/
Decrement Update Time
fUPDATE
Pin control2,3
MultiSynth output <18 MHz
Number of periods of
MultiSynth output frequency
—10
12
Periods
Spread Spectrum PP
Frequency Deviation
SSDEV
MultiSynth Output < ~Fvco/8
0.1
5.04
%
Spread Spectrum Modulation
Rate
SSDEV
MultiSynth Output < ~Fvco/8
30
635
kHz
Table 5. Performance Characteristics (Continued)
(VDD = 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Notes:
1. Outputs at integer-related frequencies and using the same driver format. See "3.10.3. Programmable Initial Phase
Offset" on page 26.
2. The maximum step size is only limited by the register lengths; however, the MultiSynth output frequency must be kept
between 5 MHz and Fvco/8.
3. Update rate via I2C is also limited by the time it takes to perform a write operation.
4. Default value is 0.5% down spread.
5. Default value is ~31.5 kHz.
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