參數(shù)資料
型號(hào)： SI5338J-A-GM
廠商： Silicon Laboratories Inc
文件頁數(shù)： 11/44頁
文件大?。?/td> 0K
描述： IC CLK GEN I2C BUS PROG 24QFN
標(biāo)準(zhǔn)包裝： 490
系列： MultiSynth™
類型： *
PLL： 是
輸入： CML，HCSL，HSCL，LVDS，LVPECL，晶體
輸出： CMOS，HCSL. HSTL. LVDS. LVPECL. SSTL
電路數(shù)： 1
比率 - 輸入:輸出： 1:4
差分 - 輸入:輸出： 是/是
頻率 - 最大： 200MHz
除法器/乘法器： 是/是
電源電壓： 1.71 V ~ 3.63 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 24-QFN（4x4）
包裝： 托盤
Si5338
Rev. 1.3
19
Synthesis of the output clocks is performed in two
stages, as shown in Figure 5. The first stage consists of
a high-frequency analog phase-locked loop (PLL) that
multiplies the input stage to a frequency within the
range of 2.2 to 2.84 GHz. Multiplication of the input
frequency is accomplished using a proprietary and
highly precise MultiSynth feedback divider (N), which
allows the PLL to generate any frequency within its
VCO range with much less jitter than typical fractional N
PLL.
Figure 5. Synthesis Stages
The second stage of synthesis consists of the output
MultiSynth dividers (MSx). Based on a fractional N
divider, the MultiSynth divider shown in Figure 6
switches seamlessly between the two closest integer
divider values to produce the exact output clock
frequency with 0 ppm error.
To eliminate phase error generated by this process, the
MultiSynth block calculates the relative phase difference
between the clock produced by the fractional-N divider
and the desired output clock and dynamically adjusts
the phase to match the ideal clock waveform. This novel
approach makes it possible to generate any output
clock frequency without sacrificing jitter performance.
This architecture allows the output of each MultiSynth to
produce any frequency from 5 to Fvco/8 MHz. To
support higher frequency operation, the MultiSynth
divider can be bypassed. In bypass mode, integer divide
ratios of 4 and 6 are supported. This allows for output
frequencies of Fvco/4 and Fvco/6 MHz, which translates
to 367–473.33 MHz and 550–710 MHz respectively.
Because each MultiSynth uses the same VCO output,
there are output frequency limitations when output
frequencies greater than Fvco/8 are desired.
For example, if 375 MHz is needed at the output of
MultiSynth0, the VCO frequency would need to be
2.25 GHz. Now, all the other MultiSynths can produce
any frequency from 5 MHz up to a maximum frequency
of 2250/8 = 281.25 MHz. MultiSynth1,2,3 could also
produce Fvco/4 = 562.5 MHz or Fvco/6 = 375 MHz. Only
two unique frequencies above Fvco/8 can be output:
Fvco/6 and Fvco/4.
Figure 6. Silicon Labs’ MultiSynth Technology
Phase
Frequency
Detector
Loop
Filter
VCO
MultiSynth
÷MS0
MultiSynth
÷MS1
MultiSynth
÷MS2
MultiSynth
÷MS3
MultiSynth
÷N
Synthesis
Stage 1
(APLL)
Synthesis
Stage 2
ref
fb
From
Input
Stage
T
o
Output
S
tage
2.2-2.84 GHz
Fractional-N
Divider
Phase
Adjust
Phase Error
Calculator
Divider Select
(DIV1, DIV2)
fVCO
fOUT
MultiSynth
相關(guān)PDF資料
PDF描述
SI5338F-A-GM IC CLK GEN I2C BUS PROG 24QFN
VE-J0X-MZ-F1 CONVERTER MOD DC/DC 5.2V 25W
VE-J0W-MZ-F4 CONVERTER MOD DC/DC 5.5V 25W
VE-J0W-MZ-F3 CONVERTER MOD DC/DC 5.5V 25W
VE-J0W-MZ-F2 CONVERTER MOD DC/DC 5.5V 25W
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SI5338J-A-GMR 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C-Program Clk Gen 0.16-200MHz inc/dec RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
SI5338J-B00190-GM 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Bulk
SI5338J-B00190-GMR 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel
SI5338J-B00380-GM 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Bulk
SI5338J-B00380-GMR 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel
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