In I2C control mode (CMODE = 0), thi" />
參數(shù)資料
型號(hào): SI5325C-C-GM
廠商: Silicon Laboratories Inc
文件頁數(shù): 51/62頁
文件大?。?/td> 0K
描述: IC UP-PROG CLK MULTIPLIER 36-QFN
標(biāo)準(zhǔn)包裝: 490
系列: DSPLL®
類型: 時(shí)鐘乘法器
PLL:
輸入: 時(shí)鐘
輸出: CML,CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 346MHz
除法器/乘法器: 是/是
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 36-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 36-QFN(6x6)
包裝: 托盤
Si5325
Rev. 0.5
55
27
SDI
I
LVCMOS
Serial Data In.
In I2C control mode (CMODE = 0), this pin is ignored.
In SPI control mode (CMODE = 1), this pin functions as the
serial data input.
This pin has a weak pulldown.
29
28
CKOUT1–
CKOUT1+
OMulti
Output Clock 1.
Differential output clock with a frequency range of 10 MHz to
1.4175 GHz. Output signal format is selected by
SFOUT1_REG register bits. Output is differential for
LVPECL, LVDS, and CML compatible modes. For CMOS for-
mat, both output pins drive identical single-ended clock out-
puts.
34
35
CKOUT2–
CKOUT2+
OMulti
Output Clock 2.
Differential output clock with a frequency range of 10 MHz to
1.4175 GHz. Output signal format is selected by
SFOUT2_REG register bits. Output is differential for
LVPECL, LVDS, and CML compatible modes. For CMOS for-
mat, both output pins drive identical single-ended clock out-
puts.
36
CMODE
I
LVCMOS
Control Mode.
Selects I2C or SPI control mode for the Si5325.
0=I2C Control Mode.
1 = SPI Control Mode.
Must not float.
GND PAD
GND
Supply
Ground Pad.
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
Table 11. Si5325 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5325 Register Map.
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