Si5325
Rev. 0.5
55
27
SDI
I
LVCMOS
Serial Data In.
In I2C control mode (CMODE = 0), this pin is ignored.
In SPI control mode (CMODE = 1), this pin functions as the
serial data input.
This pin has a weak pulldown.
29
28
CKOUT1–
CKOUT1+
OMulti
Output Clock 1.
Differential output clock with a frequency range of 10 MHz to
1.4175 GHz. Output signal format is selected by
SFOUT1_REG register bits. Output is differential for
LVPECL, LVDS, and CML compatible modes. For CMOS for-
mat, both output pins drive identical single-ended clock out-
puts.
34
35
CKOUT2–
CKOUT2+
OMulti
Output Clock 2.
Differential output clock with a frequency range of 10 MHz to
1.4175 GHz. Output signal format is selected by
SFOUT2_REG register bits. Output is differential for
LVPECL, LVDS, and CML compatible modes. For CMOS for-
mat, both output pins drive identical single-ended clock out-
puts.
36
CMODE
I
LVCMOS
Control Mode.
Selects I2C or SPI control mode for the Si5325.
0=I2C Control Mode.
1 = SPI Control Mode.
Must not float.
GND PAD
GND
Supply
Ground Pad.
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
Table 11. Si5325 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5325 Register Map.