參數(shù)資料
型號: SI5325C-C-GM
廠商: Silicon Laboratories Inc
文件頁數(shù): 48/62頁
文件大小: 0K
描述: IC UP-PROG CLK MULTIPLIER 36-QFN
標準包裝: 490
系列: DSPLL®
類型: 時鐘乘法器
PLL:
輸入: 時鐘
輸出: CML,CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 346MHz
除法器/乘法器: 是/是
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 36-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 36-QFN(6x6)
包裝: 托盤
Si5325
52
Rev. 0.5
5. Pin Descriptions: Si5325
Table 11. Si5325 Pin Descriptions
Pin #
Pin Name
I/O
Signal Level
Description
1RST
ILVCMOS
External Reset.
Active low input that performs external hardware reset of
device. Resets all internal logic to a known state and forces
the device registers to their default value. Clock outputs are
tristated during reset. The part must be programmed after a
reset or power-on to get a clock output. See Family Refer-
ence Manual for details.
This pin has a weak pull-up.
2, 7, 9, 14,
18, 30, 33
NC
No Connect.
This pin must be left unconnected for normal operation.
3
INT_C1B
O
LVCMOS
Interrupt/CKIN1 Invalid Indicator.
This pin functions as a device interrupt output or an alarm
output for CKIN1. If used as an interrupt output, INT_PIN
must be set to 1. The pin functions as a maskable interrupt
output with active polarity controlled by the INT_POL register
bit.
If used as an alarm output, the pin functions as a LOS (and
optionally FOS) alarm indicator for CKIN1. Set
CK1_BAD_PIN = 1 and INT_PIN =0.
0 = CKIN1 present.
1 = LOS (FOS) on CKIN1.
The active polarity is controlled by CK_BAD_POL. If no func-
tion is selected, the pin tristates.
Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Si5325 Register Map.
1
2
3
29
30
31
32
33
34
35
36
20
21
22
23
24
25
26
27
10 11 12 13 14 15 16 17
4
5
6
7
8
NC
RST
C2B
INT_C1B
GND
VDD
GND
VD
D
VD
D
CL
KI
N2
+
CL
K
IN2
NC
VD
D
CLKI
N1+
CL
K
IN1
CS_CA
SCL
SDA_SDO
A1
A2_SS
SDI
CL
KO
U
T
1
NC
GND
VD
D
NC
CKO
U
T
2
CKO
U
T
2
+
CM
ODE
GND
Pad
A0
GND
9
18
19
28
NC
GND
CL
K
O
UT1+
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