VOH IO = –2 mA VDD
參數(shù)資料
型號(hào): SI5319C-C-GMR
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 49/50頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK MULT/ATTENUATOR 36QFN
標(biāo)準(zhǔn)包裝: 250
系列: DSPLL®
類型: 時(shí)鐘/頻率倍增器,抖動(dòng)衰減器,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH
輸入: 時(shí)鐘,晶體
輸出: CML,CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 是/是
頻率 - 最大: 346MHz
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 36-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 36-QFN(6x6)
包裝: 帶卷 (TR)
Si5319
8
Rev. 1.0
Output Voltage High
VOH
IO = –2 mA
VDD =1.71V
VDD –0.4
V
Output Voltage High
IO = –2 mA
VDD =2.97V
VDD –0.4
V
Disabled Leakage
Current
IOZ
RSTb = 0
–100
100
A
Table 3. Microprocessor Control
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
I2C Bus Lines (SDA, SCL)
Input Voltage Low
VILI2C
0.25 x VDD
V
Input Voltage High
VIHI2C
0.7 x VDD
—VDD
V
Input Current
III2C
VIN = 0.1 x VDD
to 0.9 x VDD
–10
10
A
Hysteresis of Schmitt
trigger inputs
VHYSI2C
VDD = 1.8V
0.1 x VDD
——
V
VDD = 2.5 or 3.3 V
0.05 x VDD
——
V
Output Voltage Low
VOLI2C
VDD =1.8 V
IO = 3 mA
0.2 x VDD
V
VDD = 2.5 or 3.3 V
IO = 3 mA
——
0.4
V
SPI Specifications
Duty Cycle, SCLK
tDC
SCLK = 10 MHz
40
60
%
Cycle Time, SCLK
tc
100
ns
Rise Time, SCLK
tr
20–80%
25
ns
Fall Time, SCLK
tf
20–80%
25
ns
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Notes:
1.
Current draw is independent of supply voltage.
2.
No under- or overshoot is allowed.
3.
LVPECL outputs require nominal VDD ≥ 2.5 V.
4.
This is the amount of leakage that the 3-level inputs can tolerate from an external driver. See Si53xx Family
Reference Manual for more details.
5.
LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
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