VIL V
參數(shù)資料
型號: SI5319C-C-GMR
廠商: Silicon Laboratories Inc
文件頁數(shù): 48/50頁
文件大?。?/td> 0K
描述: IC CLOCK MULT/ATTENUATOR 36QFN
標(biāo)準(zhǔn)包裝: 250
系列: DSPLL®
類型: 時(shí)鐘/頻率倍增器,抖動(dòng)衰減器,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH
輸入: 時(shí)鐘,晶體
輸出: CML,CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 是/是
頻率 - 最大: 346MHz
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 36-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 36-QFN(6x6)
包裝: 帶卷 (TR)
Si5319
Rev. 1.0
7
2-Level LVCMOS Input Pins
Input Voltage Low
VIL
VDD =1.71V
0.5
V
VDD =2.25V
0.7
V
VDD =2.97V
0.8
V
Input Voltage High
VIH
VDD =1.89V
1.4
V
VDD =2.25 V
1.8
V
VDD =3.63V
2.5
V
3-Level Input Pins4
Input Voltage Low
VILL
0.15 x VDD
V
Input Voltage Mid
VIMM
0.45 x
VDD
—0.55 x VDD
V
Input Voltage High
VIHH
0.85 x
VDD
——
V
Input Low Current
IILL
See Note 4
–20
A
Input Mid Current
IIMM
See Note 4
–2
+2
A
Input High Current
IIHH
See Note 4
20
A
LVCMOS Output Pins
Output Voltage Low
VOL
IO = 2 mA
VDD =1.71V
——
0.4
V
Output Voltage Low
IO = 2 mA
VDD =2.97V
——
0.4
V
Table 2. DC Characteristics (Continued)
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Notes:
1.
Current draw is independent of supply voltage.
2.
No under- or overshoot is allowed.
3.
LVPECL outputs require nominal VDD ≥ 2.5 V.
4.
This is the amount of leakage that the 3-level inputs can tolerate from an external driver. See Si53xx Family
Reference Manual for more details.
5.
LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
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