參數(shù)資料
型號: SI5316-C-GM
廠商: Silicon Laboratories Inc
文件頁數(shù): 11/26頁
文件大?。?/td> 0K
描述: IC PREC JITTER ATTENUATOR 36-QFN
標(biāo)準(zhǔn)包裝: 490
系列: DSPLL®
類型: 時鐘振動衰減器
PLL: 帶旁路
輸入: 時鐘
輸出: CML,CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:1
差分 - 輸入:輸出: 是/是
頻率 - 最大: 710MHz
除法器/乘法器: 是/無
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 36-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 36-QFN(6x6)
包裝: 托盤
Si5316
Rev. 1.0
19
33
30
SFOUT0
SFOUT1
I
3-Level*
Signal Format Select.
Three level inputs that select the output signal format (common
mode voltage and differential swing) for CKOUT. Valid settings
include LVPECL, LVDS, and CML. Also includes selections for
CMOS mode, tristate mode, and tristate/sleep mode.
These pins have both weak pull-ups and weak pull-downs and
default to M.
Some designs may require an external resistor voltage divider when
driven by an active device that will tri-state.
34
35
CKOUT–
CKOUT+
OMulti
Clock Output.
Differential output clock with a frequency selected from a table of
values. Output signal format is selected by SFOUT pins. Output is
differential for LVPECL, LVDS, and CML compatible modes. For
CMOS format, both output pins drive identical single-ended clock
outputs.
GND PAD
GND
Supply
Ground Pad.
The ground pad must provide a low thermal and electrical
impedance to a ground plane.
Table 8. Si5316 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
*Note: Denotes 3-Level input pin with states designated as L (ground), M (VDD/2), and H (VDD).
SFOUT[1:0]
Signal Format
HH
Reserved
HM
LVDS
HL
CML
MH
LVPECL
MM
Reserved
ML
LVDS—low swing
LH
CMOS
LM
Disabled
LL
Reserved
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