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參數(shù)資料
| 型號： | SI5023-D-GM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 16/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK/DATA RECVRY W/AMP 28MLP |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | DSPLL® |
| 類型： | 時鐘和數(shù)據(jù)恢復(fù)（CDR） |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，ATM 應(yīng)用 |
| 輸入： | 時鐘 |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.7GHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 28-QFN（5x5） |
| 包裝： | 管件 |
| 其它名稱： | 336-1276 |
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Si5023
Rev. 1.3
23
5
6
REFCLK+
REFCLK–
ISee Table 2
Differential Reference Clock (Optional).
When present, the reference clock sets the center
operating frequency of the DSPLL for clock and
data recovery. Tie REFCLK+ to VDD and REFCLK–
to GND to operate without an external reference
clock.
See Table 8 for typical reference clock frequencies.
7
LOL
OLVTTL
Loss-of-Lock.
This output is driven low when the recovered clock
frequency deviates from the reference clock by the
amount specified in Table 4 on page 9. If no exter-
nal reference is supplied, this signal will be active
when the internal PLL is no longer locked to the
incoming data.
8
LTR
ILVTTL
Lock-to-Reference.
When this pin is low, the DSPLL disregards the data
inputs. If an external reference is supplied, the out-
put clock is locked to the supplied reference. If no
external reference is used, the DSPLL locks the
control loop until LTR is released.
Note: This input has a weak internal pullup.
9
LOS
OLVTTL
Loss-of-Signal.
This output pin is driven low when the input signal is
below the threshold set via LOS_LVL. (LOS opera-
tion is guaranteed only when ac coupling is used on
the DIN inputs.)
10
DSQLCH
LVTTL
Data Squelch.
When driven high, this pin forces the data present
on DOUT+ = 0 and DOUT– = 1. For normal opera-
tion, this pin should be low. DSQLCH may be used
during LOS/LOL conditions to prevent random data
from being presented to the system.
Note: This input has a weak internal pulldown.
11,14,18,21,
25
VDD
3.3 V
Supply Voltage.
Nominally 3.3 V.
12
13
DIN+
DIN–
ISee Table 2
Differential Data Input.
Clock and data are recovered from the differential
signal present on these pins. AC coupling is recom-
mended.
15
GND
Production Test Input.
This pin is used during production testing and must
be tied to GND for normal operation.
16
17
DOUT–
DOUT+
OCML
Differential Data Output.
The data output signal is a retimed version of the
data recovered from the signal present on DIN.
Table 9. Si5023 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
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