參數(shù)資料
型號: SI5010-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 4/20頁
文件大小: 0K
描述: BOARD EVALUATION FOR SI5010
標(biāo)準(zhǔn)包裝: 1
主要目的: 計時,時鐘和數(shù)據(jù)恢復(fù)(CDR)
已用 IC / 零件: SI5010
已供物品:
其它名稱: 336-1121
Si5010
12
Rev. 1.4
4.10. Differential Input Circuitry
The Si5010 provides differential inputs for both the high-speed data (DIN) and the reference clock (REFCLK)
inputs. An example termination for these inputs is shown in Figure 6. In applications where direct dc coupling is
possible, the 0.1 F capacitors may be omitted. The DIN and REFCLK input amplifiers require an input signal with
a minimum differential peak-to-peak voltage listed in Table 2 on page 6.
Figure 6. Input Termination for DIN and REFCLK (AC Coupled)
Figure 7. Single-Ended Input Termination for REFCLK (AC Coupled)
Figure 8. Single-Ended Input Termination for DIN (AC Coupled)
Differential
Driver
Si5010
0.1 F
Zo = 50
Zo = 50
DIN+,
REFCLK+
DIN–,
REFCLK–
2.5 k
2.5 k
10 k
10 k
102
VDD
GND
0.1 F
0.1
μF
Clock
source
Si5010
0.1
μF
Zo = 50
Ω
REFCLK +
REFCLK –
2.5 k
Ω
2.5 k
Ω
10 k
Ω
10 k
Ω
100
Ω
GND
VDD
102
Ω
0.1
μF
Clock
source
Si5010
0.1
μF
Zo = 50
Ω
DIN +
DIN –
2.5 k
Ω
2.5 k
Ω
10 k
Ω
10 k
Ω
100
Ω
GND
VDD
102
Ω
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