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參數(shù)資料
| 型號： | SI5010-EVB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 17/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR SI5010 |
| 標準包裝： | 1 |
| 主要目的： | 計時，時鐘和數(shù)據(jù)恢復(fù)（CDR） |
| 已用 IC / 零件： | SI5010 |
| 已供物品： | 板 |
| 其它名稱： | 336-1121 |
Si5010
6
Rev. 1.4
Table 2. DC Characteristics
(VDD =2.5 V ±5%, TA = –40°C to 85°C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Supply Current
OC-12
OC-3
IDD
—
117
124
131
138
mA
Power Dissipation
OC-12
OC-3
PD
—
293
310
344
362
mW
Common Mode Input Voltage (DIN, REFCLK)
VICM
varies with VDD
—.80 x VDD
—V
Single Ended Input Voltage (DIN, REFCLK)
VIS
See Figure 1
200
—
750
mVPP
Differential Input Voltage Swing*
(DIN, REFCLK)
VID
See Figure 1
200
—
1500
mVPP
Input Impedance (DIN, REFCLK)
RIN
Line-to-Line
84
100
116
Ω
Differential Output Voltage Swing
(DOUT)
VOD
100
Ω Load
Line-to-Line
780
970
1260
mVPP
Differential Output Voltage Swing
(CLKOUT)
VOD
100
Ω Load
Line-to-Line
780
970
1260
mVPP
Output Common Mode Voltage
(DOUT,CLKOUT)
VOCM
100
Ω Load
Line-to-Line
—VDD –
0.23
—V
Output Impedance (DOUT,CLKOUT)
ROUT
Single-ended
84
100
116
Ω
Output Short to GND (DOUT,CLKOUT)
ISC(–)
—2531
mA
Output Short to VDD (DOUT,CLKOUT)
ISC(+)
–17.5
–14.5
—
mA
Input Voltage Low (LVTTL Inputs)
VIL
——
.8
V
Input Voltage High (LVTTL Inputs)
VIH
2.0
—
V
Input Low Current (LVTTL Inputs)
IIL
——
10
μA
Input High Current (LVTTL Inputs)
IIH
——
10
μA
Output Voltage Low (LVTTL Outputs)
VOL
IO =2mA
—
0.4
V
Output Voltage High (LVTTL Outputs)
VOH
IO =2mA
2.0
—
V
Input Impedance (LVTTL Inputs)
RIN
10
—
k
Ω
PWRDN/CAL Leakage Current
IPWRDN
VPWRDN ≥ 0.8 V
15
25
35
μA
*Note: The DIN and REFCLK inputs may be driven differentially or single-endedly. When driving single-endedly, the voltage
swing of the signal applied to the active input must exceed the specified minimum differential input voltage swing (VID
min) and the unused input must be ac-coupled to ground. When driving differentially, the difference between the positive
and negative input signals must exceed VID min. (Each individual input signal needs to swing only half of this range.) In
either case, the voltage applied to any individual pin (DIN+, DIN–, REFCLK+, or REFCLK–) must not exceed the
specified maximum Input Voltage Range (VIS max).
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