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| 型號： | Si4133G-BT* |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | DUAL-BAND RF SYNTHESIZER WITH INTEGRATED VCOS FOR GSM AND GPRS WIRELESS COMMUNICATIONS |
| 中文描述： | 雙波段射頻合成器集成的GSM和GPRS無線通訊和VCO |
| 文件頁數(shù)： | 8/32頁 |
| 文件大小： | 466K |
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Si4133G
8
Rev. 1.1
Table 5. RF and IF Synthesizer Characteristics
(V
DD
= 2.7 to 3.6 V, T
A
= –20 to 85°C)
Parameter
1
XIN Input Frequency
Reference Amplifier Sensitivity
Symbol
f
REF
V
REF
Test Condition
Min
—
0.5
Typ
13
—
Max
—
V
DD
+0.3
Unit
MHz
V
PP
Phase Detector Update Frequency
RF1 Center Frequency Range
RF2 Center Frequency Range
IF VCO Center Frequency
Tuning Range from f
CEN
RF1 VCO Pushing
RF2 VCO Pushing
IF VCO Pushing
RF1 VCO Pulling
RF2 VCO Pulling
IF VCO Pulling
RF1 Phase Noise
f
φ
f
φ
= f
REF
/R
200
—
—
—
—
0.5
0.4
0.3
0.4
0.1
0.1
–132
–142
0.9
–134
–144
0.7
–117
0.4
–26
–26
–26
–2
–6
–70
–75
–80
–75
–80
–80
140
KHz
MHz
MHz
MHz
%
MHz/V
MHz/V
MHz/V
MHz
PP
MHz
PP
MHz
PP
dBc/Hz
dBc/Hz
deg rms
dBc/Hz
dBc/Hz
deg rms
dBc/Hz
deg rms
dBc
dBc
dBc
dBm
dBm
dBc
dBc
dBc
dBc
dBc
dBc
μ
s
f
CEN
f
CEN
f
CEN
947
789
526
–5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
–7
–8
—
—
—
—
—
—
—
1720
1429
952
5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
–1
—
—
—
—
—
—
—
Note: L
EXT
±10%
Open loop
VSWR = 2:1, all
phases, open loop
1 MHz offset
3 MHz offset
100 Hz to 100 kHz
1 MHz offset
3 MHz offset
100 Hz to 100 kHz
100 kHz offset
100 Hz to 100 kHz
Second Harmonic
RF1 Integrated Phase Error
RF2 Phase Noise
RF2 Integrated Phase Error
IF Phase Noise
IF Integrated Phase Error
RF1 Harmonic Suppression
RF2 Harmonic Suppression
IF Harmonic Suppression
RFOUT Power Level
IFOUT Power Level
RF1 Reference Spurs
Z
L
= 50
Z
L
= 50
Offset = 200 kHz
Offset = 400 kHz
Offset = 600 kHz
Offset = 200 kHz
Offset = 400 kHz
Offset = 600 kHz
Figures 4, 5
R
F2 Reference Spurs
Power Up Request to Synthesizer
Ready Time, RF1, RF2, IF
2
Power Down Request to Synthesizer Off
Time
3
Notes:
1.
RF1 = 1.55 GHz, RF2 = 1.2 GHz, IF
=
550 MHz for all parameters unless otherwise noted.
2.
From power up request (PWDNB
↑
or SENB
↑
during a write of 1 to bits PDIB and PDRB in Register 2) to RF and IF
synthesizers ready (settled to within 0.1 ppm frequency error). Typical settling time to 5 degrees phase error is 120
μ
s.
3.
From power down request (PWDNB
↓
, or SENB
↑
during a write of 0 to bits PDIB and PDRB in Register 2) to supply
current equal to I
PWDN
.
t
pup
t
pdn
Figures 4, 5
—
—
100
ns
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