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參數(shù)資料
| 型號： | Si4113G-BT* |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | DUAL-BAND RF SYNTHESIZER WITH INTEGRATED VCOS FOR GSM AND GPRS WIRELESS COMMUNICATIONS |
| 中文描述： | 雙波段射頻合成器集成的GSM和GPRS無線通訊和VCO |
| 文件頁數(shù)： | 17/32頁 |
| 文件大?。?/td> | 466K |
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Si4133G
Rev. 1.1
17
either the IF or RF PLL nears the limit of its
compensation range (LDETB will also be high when
either PLL is executing the self-tuning algorithm). The
output frequency will still be locked when LDETB goes
high, but the PLL will eventually lose lock if the
temperature continues to drift in the same direction.
Therefore, if LDETB goes high both the IF and RF PLLs
should promptly be re-tuned by initiating the self-tuning
algorithm.
Output Frequencies
The IF and RF output frequencies are set by
programming the N-Divider registers. Each RF PLL has
its own N register and can be programmed
independently. All three PLL R dividers are fixed at
R = 65 to yield a 200 kHz phase detector update rate
from a 13 MHz reference frequency. Programming the
N-Divider register for either RF1 or RF2 automatically
selects the associated output.
The reference frequency on the XIN pin is divided by R
and this signal is the input to the PLL’s phase detector.
The other input to the phase detector is the PLL’s VCO
output frequency divided by N. The PLL works to make
these frequencies equal. That is, after an initial transient
or
For XIN = 13 MHz this simplifies to
The integer N is set by programming the RF1 N-Divider
register (Register 3), the RF2 N-Divider register
(Register 4), and the IF N-Divider register (Register 5).
Each N divider is implemented as a conventional high
speed divider. That is, it consists of a dual-modulus
prescaler, a swallow counter, and a lower speed
synchronous counter. However, the calculation of these
values is done automatically. Only the appropriate N
value needs to be programmed.
PLL Loop Dynamics
The transient response for each PLL has been
optimized for a GSM application. VCO gain, phase
detector gain, and loop filter characteristics are not
programmable.
The settling time for each PLL is directly proportional to
its phase detector update period T
φ
(T
φ
equals 1/f
φ
). For
a GSM application with a 13 MHz reference frequency,
the RF and IF PLLs T
φ
= 5
μ
S. During the first 6.5
update periods, the Si4133G executes the self-tuning
algorithm. Thereafter the PLL controls the output
frequency. Because of the unique architecture of the
Si4133G PLLs, the time required to settle the output
frequency to 0.1 ppm error is approximately 21 update
periods. Thus, the total time after power-up or a change
in programmed frequency until the synthesized
frequency is well settled (including time for self-tuning)
is around 28 update periods or 140
μ
S.
RF and IF Outputs (RFOUT and IFOUT)
The RFOUT pin is driven by an amplifier that buffers the
output pin from the RF VCOs, and must be coupled to
its load through an AC coupling capacitor. The amplifier
receives its input from either the RF1 or RF2 VCO,
depending upon which N-Divider register was last
written. For example, programming the N-Divider
register for RF1 automatically selects the RF1 VCO
output.
A matching network is required to maximize power
delivered into a 50
load. The network consists of a 2
nH series inductance, which may be realized with a PC
board trace, connected between the RFOUT pin and
the AC coupling capacitor. The network is made to
provide an adequate match for both the RF1 and RF2
frequency bands, and also filters the output signal to
reduce harmonic distortion. A 50
load is not required
for proper operation of the Si4133G. Depending on
transceiver requirements, the matching network may
not be needed. See Figure 16.
Figure 16. RFOUT 50
Test Circuit
The IFOUT pin is driven by an amplifier that buffers the
output pin from the IF VCO. The IFOUT pin must be
coupled to its load through an AC coupling capacitor. A
matching network is required to maximize power
delivered into a 50
load. See Figure 17.
f
N
-----------
f
65
-----------
=
f
OUT
65
------
f
REF
=
f
OUT
N 200 kHz
=
RFOUT
2 nH
560 pF
50
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