(VDD
參數(shù)資料
型號： SI3232-G-GQ
廠商： Silicon Laboratories Inc
文件頁數(shù)： 107/128頁
文件大?。?/td> 0K
描述： IC SLIC PROG DUAL-CH 64TQFP
標(biāo)準(zhǔn)包裝： 160
功能： 用戶線路接口概念（SLIC）
接口： ISDN
電路數(shù)： 2
電源電壓： 3.13 V ~ 3.47 V
電流 - 電源： 28mA
功率（瓦特）： 280mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-TQFP
供應(yīng)商設(shè)備封裝： 64-TQFP（10x10）
包裝： 托盤
Si3232
8
Preliminary Rev. 0.96
Not
Recommended
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Table 4. AC Characteristics
(VDD, VDD1–VDD4 = 3.13 to 3.47 V, TA = 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade)
Parameter
Test Condition
Min
Typ
Max
Unit
TX/RX Performance
TX Full Scale Output
VTXP–XTXN
0.1
—VDD–0.1
V
RX Full Scale Input
VRXP–VRXN, ARX = 0 dB
ARX = –3.52 dB
ARX = –6.02 dB
0.25
0
—
VDD–0.25
VDD
V
Analog Input/Output Common
Mode Voltage
CMTXSEL = 1
CMTXSEL = 0
0.6
—
1.5
—
V
Overload Level
ATX stage = 0 dB, THD = 1.5%
2.5
—
VPK
Overload Compression
—
Single Frequency Distortion1
2-wire to 4-wire or 4-wire to 2-wire:
200 Hz–3.4 kHz
—
–74
–68
dB
2-wire to 4-wire to 2-wire:
200 Hz–3.4 kHz
—
–74
–65
dB
Signal-to-(Noise + Distortion)
Ratio2
200 Hz–3.4 kHz
Active off-hook, and OHT, any ZT
—
–74
–68
Intermodulation Distortion
—
–41
dB
Gain Accuracy2
2-Wire to 4-Wire or 4-Wire to 2-Wire,
1014 Hz, Any gain setting
–0.25
—
+0.25
dB
Gain Distortion vs. Frequency
–3 dB corners
0.01
—
10
kHz
Gain Tracking
1014 Hz sine wave,
reference level –10 dBm
signal level:
3dB to –37dB
–37dB to –50dB
–50dB to –60dB
—
±0.25
±0.5
±1.0
dB
Crosstalk between channels
TX or RX to TX
TX to RX to RX
0 dBm0,
300Hz to 3.4kHz
—
–75
dB
2-Wire Return Loss3
200Hz to 3.4kHz
26
30
—
dB
Notes:
1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should
be –10 dBm0. The output signal magnitude at any other frequency will be smaller than the maximum value
specified.
2. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching.
3. VDD = 3.3 V, VBAT = –52 V, no fuse resistors, RL = 600 , ZS = 600 synthesized using RS register coefficients.
4. The level of any unwanted tones within the bandwidth of 0 to 4 kHz will not exceed –55 dBm.
5. The OBIAS and ABIAS registers program the dc bias current through the SLIC in the on-hook transmission and off-
hook active conditions, respectively. This per-pin total current setting should be selected such that it can
accommodate the sum of the metallic and longitudinal currents through each of the TIP and RING leads for a given
application.
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