參數(shù)資料
型號(hào)： SI3216MDCQ1-EVB
廠(chǎng)商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 49/122頁(yè)
文件大小： 0K
描述： DAUGHTER CARD W/SI3201 INTERFACE
標(biāo)準(zhǔn)包裝： 1
系列： ProSLIC®
類(lèi)型： ADC + DAC，編碼解碼器，前端
適用于相關(guān)產(chǎn)品： Si3216
所含物品： 評(píng)估板和光盤(pán)
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Si3216
32
Rev. 1.0
Not
Recommended
fo
r N
ew
D
esi
gn
s
Figure 18. Loop Closure Detection
2.1.6. Loop Closure Detection
A loop closure event signals that the terminal equipment
has gone off-hook during On-Hook Transmission or On-
Hook Active states. The ProSLIC performs loop closure
detection
digitally
using
its
on-chip
monitor
A/D
converter. The functional blocks required to implement
loop closure detection are shown in Figure 18. The
primary input to the system is the Loop Current Sense
value provided in the LCS register (direct Register 79).
The LCS value is processed in the Input Signal
Processor when the ProSLIC is in the On-Hook
Transmission or On-Hook Active Linefeed state, as
indicated by the Linefeed Shadow register, LFS[2:0]
(direct Register 64). The data then feeds into a
programmable digital low-pass filter, which removes
unwanted ac signal components before threshold
detection.
The output of the low-pass filter is compared to a
programmable threshold, LCRT (indirect Register 15).
The threshold comparator output feeds a programmable
debouncing filter. The output of the debouncing filter
remains in its present state unless the input remains in
the opposite state for the entire period of time
programmed by the loop closure debounce interval,
LCDI (direct Register 69). If the debounce interval has
been satisfied, the LCR bit will be set to indicate that a
valid loop closure has occurred. A loop closure interrupt
is generated if enabled by the LCIE bit (direct
Register 22). Table 25 lists the registers that must be
written or monitored to correctly detect a loop closure
condition.
2.1.7. Loop Closure Threshold Hysteresis
Programmable hysteresis to the loop closure threshold
can
be
enabled
by
setting
HYSTEN = 1
(direct
Register 108, bit 0). The hysteresis is defined by LCRT
(indirect Register 15) and LCRTL (indirect Register 66),
which set the upper and lower bounds, respectively.
2.1.8. Voltage-Based Loop Closure Detection
An optional voltage-based loop closure detection mode
is enabled by setting LCVE = 1 (direct Register 108,
bit 2). In this mode, the loop voltage is compared to the
loop
closure
threshold
register
(LCRT),
which
represents a minimum voltage threshold instead of a
maximum current threshold. If hysteresis is also
enabled, then LCRT represents the upper voltage
boundary and LCRTL represents the lower voltage
boundary for hysteresis. Although voltage-based loop
closure detection is an option, the default current-based
loop closure detection is recommended.
ISP_OUT
NCLR
LCDI
Input
Signal
Processor
Digital
LPF
Loop Closure
Threshold
D ebounce
Filter
+
–
LCR
LCIP
LCIE
Interrupt
Logic
LCS
LVS
LCVE
LFS
LCRTL
LCRT
HYSTEN
Table 25. Register Set for Loop
Closure Detection
Parameter
Register
Location
Loop Closure
Interrupt Pending
LCIP
Direct Reg.19
Loop Closure
Interrupt Enable
LCIE
Direct Reg. 22
Loop Closure Threshold
LCRT[5:0]
Indirect Reg.15
Loop Closure
Threshold—Lower
LCRTL[5:0]
Indirect Reg. 66
Loop Closure Filter
Coefficient
NCLR[12:0]
Indirect Reg. 22
Loop Closure Detect
Status (monitor only)
LCR
Direct Reg. 68
Loop Closure Detect
Debounce Interval
LCDI[6:0]
Direct Reg. 69
Hysteresis Enable
HYSTEN
Direct Reg. 108
Voltage-Based Loop
Closure
LCVE
Direct Reg. 108
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