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參數(shù)資料
型號(hào)： SI3216MDCQ1-EVB
廠商： Silicon Laboratories Inc
文件頁數(shù)： 33/122頁
文件大?。?/td> 0K
描述： DAUGHTER CARD W/SI3201 INTERFACE
標(biāo)準(zhǔn)包裝： 1
系列： ProSLIC®
類型： ADC + DAC，編碼解碼器，前端
適用于相關(guān)產(chǎn)品： Si3216
所含物品： 評(píng)估板和光盤
Si3216
18
Rev. 1.0
Not
Recommended
fo
r N
ew
D
esi
gn
s
Table 10. Switching Characteristics—General Inputs
VDDA =VDDA = 3.13 to 5.25 V, TA = 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade, CL =20pF)
Parameter
Symbol
Min
Typ
Max
Unit
Rise Time, RESET
tr
——
20
ns
RESET Pulse Width
trl
100
—
ns
Note: All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are
VIH =VD – 0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.
Table 11. Switching Characteristics—SPI
VDDA =VDDA = 3.13 to 5.25 V, TA = 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade, CL =20pF
Parameter
Symbol
Test
Conditions
Min
Typ
Max
Unit
Cycle Time SCLK
tc
0.062
—
s
Rise Time, SCLK
tr
—
25
ns
Fall Time, SCLK
tf
—
25
ns
Delay Time, SCLK Fall to SDO Active
td1
—
20
ns
Delay Time, SCLK Fall to SDO
Transition
td2
—
20
ns
Delay Time, CS Rise to SDO Tri-state
td3
—
20
ns
Setup Time, CS to SCLK Fall
tsu1
25
—
ns
Hold Time, CS to SCLK Rise
th1
20
—
ns
Setup Time, SDI to SCLK Rise
tsu2
25
—
ns
Hold Time, SDI to SCLK Rise
th2
20
—
ns
Delay Time between Chip Selects
(Continuous SCLK)
tcs
440
—
ns
Delay Time between Chip Selects
(Non-continuous SCLK)
tcs
220
—
ns
SDI to SDITHRU Propagation Delay
td4
—
4
10
ns
Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH =VDDD –0.4 V, VIL =0.4 V
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