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參數(shù)資料
| 型號(hào)： | SI3200-KS |
| 廠(chǎng)商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 73/128頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC LINEFEED INTRFC 100V 16SOIC |
| 標(biāo)準(zhǔn)包裝： | 48 |
| 系列： | ProSLIC® |
| 功能： | 用戶(hù)線(xiàn)路接口概念（SLIC），CODEC |
| 接口： | GCI，PCM，SPI |
| 電路數(shù)： | 2 |
| 電源電壓： | 3.3V，5V |
| 電流 - 電源： | 110µA |
| 功率（瓦特）： | 941mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm Width）裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC N |
| 包裝： | 管件 |
| 包括： | 電池切換，BORSCHT 功能，DTMF 生成和解碼，F(xiàn)SK 音調(diào)生成，調(diào)制解調(diào)器和傳真音調(diào)檢測(cè) |
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Si3232
Preliminary Rev. 0.96
49
Not
Recommended
fo
r N
ew
D
esi
gn
s
The resulting gain levels using the ARX stage are
summarized in Table 30. All settings assume an
external codec with 475
per leg of source impedance
driving the RX inputs differentially at VRXPa-VRXNa
(for channel a) or VRXPb-VRXNb (for channel b) to
achieve a 0 dBm0 TIP-RING audio output signal.
4.15. System Clock Generation
The Si3232 generates the necessary internal clock
frequencies from the PCLK input. PCLK must be
synchronous to the 8 kHz FSYNC clock and run at one
of the following rates: 256kHz, 512kHz, 786kHz,
1.024 MHz,
1.536 MHz,
1.544 MHz,
2.048 MHz,
4.096 MHz, or 8.192 MHz. The ratio of the PCLK rate to
the FSYNC rate is determined by a counter clocked by
PCLK. The 3-bit ratio information is automatically
transferred
into
an
internal
register,
PLL_MULT,
following a device reset. PLL_MULT is used to control
the internal PLL, which multiplies PCLK as needed to
generate the rate required to run the internal filters and
other circuitry.
The PLL clock synthesizer settles quickly after powerup
or update of the PLL-MULT register. The PLL lock
process begins immediately after the RESET pin is
pulled high and will take approximately 5 ms to achieve
lock after RESET is released with stable PCLK and
FSYNC. However, the settling time depends on the
PCLK frequency and can be predicted based on the
following equation:
tSETTLE =64 / fPCLK
Note: Therefore, the RESET pin must be held low during
powerup and should only be released when both PCLK
and FSYNC signals are known to be stable.
4.15.1. Interrupt Logic
The Si3232 is capable of generating interrupts for the
following events:
Loop current/ring ground detected.
Ground key detected.
Ring trip detected.
Power alarm.
Ringing active timer expired.
Ringing inactive timer expired.
Pulse metering active timer expired.
Pulse metering inactive timer expired.
RAM address access complete.
The interface to the interrupt logic consists of six
registers. Three interrupt status registers (IRQ0–IRQ3)
contain one bit for each of the above interrupt functions.
These bits are set when an interrupt is pending for the
associated resource. Three interrupt mask registers
(IRQEN1–IRQEN3) also contain one bit for each
interrupt function. In the case of the interrupt mask
registers, the bits are active high. Refer to the
appropriate functional description text for operational
details of the interrupt functions.
Figure 26. PLL Frequency Synthesizer
Table 30. ARX Attenuation Stage Settings
ARXMUTE
Setting
ARX[1:0]
Setting
Typical TX Path Gain
1
Mute (no T-R output)
000
0 dB (G = 1)
0
01
–3.52 dB (G = 2/3)
0
10
–6.02 dB (G = 1/2)
0
11
Reserved. Do not use.
PFD
DIV M
PLL_MULT
VCO
÷2
RESET
28.672 MHz
PCLK
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