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| 型號： | SI3025 |
| 廠商： | Allegro MicroSystems, Inc. |
| 英文描述： | COOLER FOR TO-3 20 WATTS |
| 中文描述： | 低電壓，高電流線性穩(wěn)壓器1.8伏 |
| 文件頁數(shù)： | 7/54頁 |
| 文件大?。?/td> | 1407K |
| 代理商： | SI3025 |
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Si3035
Rev. 1.2
7
Figure 2. General Inputs Timing Diagram
Table 6. Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
DC Supply Voltage
V
D
, V
A
–0.5 to 6.0
V
Input Current, Si3021 Digital Input Pins
I
IN
±10
mA
Digital Input Voltage
V
IND
–0.3 to (V
D
+ 0.3)
V
Operating Temperature Range
T
A
–40 to 100
°C
Storage Temperature Range
T
STG
–65 to 150
°C
Note:
Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Table 7. Switching Characteristics—General Inputs
(V
A
= Charge Pump, V
D
= 3.0 to 5.25 V, T
A
= 0 to 70°C for K-Grade, C
L
= 20 pF)
Parameter
1
Symbol
Min
Typ
Max
Unit
Cycle Time, MCLK
t
mc
16.67
—
1000
ns
MCLK Duty Cycle
t
dty
40
50
60
%
Rise Time, MCLK
t
r
—
—
5
ns
Fall Time, MCLK
t
f
—
—
5
ns
MCLK Before RESET
↑
RESET Pulse Width
2
t
mr
10
—
—
cycles
t
rl
250
—
—
ns
M0, M1 Before RESET
↑
3
t
mxr
150
—
—
ns
Notes:
1.
All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are
V
IH
= V
D
– 0.4 V, V
IL
= 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.
2.
The minimum RESET pulse width is the greater of 250 ns or 10 MCLK cycle times.
3.
M0 and M1 are typically connected to V
D
or GND and should not be changed during normal operation.
MCLK
M0, M1
t
r
RESET
t
mc
t
mr
t
f
t
mxr
V
IH
V
IL
t
rl
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