參數(shù)資料
型號: SI3025
廠商: Allegro MicroSystems, Inc.
英文描述: COOLER FOR TO-3 20 WATTS
中文描述: 低電壓,高電流線性穩(wěn)壓器1.8伏
文件頁數(shù): 39/54頁
文件大小: 1407K
代理商: SI3025
Si3035
Rev. 1.2
39
Reset settings = 0000_0000 (serial mode 0, 1)
Reset settings = 0001_0011 (serial mode 2)
Reset settings = 0000_0000 (serial mode 0, 1, 2)
Reset settings = 0000_0000
Register 8. PLL1 Multiply M1
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
M1[7:0]
Type
R/W
Bit
Name
Function
7:0
M1[7:0]
M1 Multiplier.
Contains the (value – 1) for determining the output frequency on PLL1
Register 9. PLL2 Divide/Multiply N2/M2
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
N2[3:0]
M2[3:0]
Type
R/W
R/W
Bit
Name
Function
7:4
N2[3:0]
N2 Divider.
Contains the (value – 1) for determining the output frequency on PLL2.
3:0
M2[3:0]
M2 Multiplier.
Contains the (value – 1) for determining the output frequency on PLL2.
Register 10. PLL Control Register
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
CGM
Type
R/W
Bit
Name
Function
7:1
Reserved
Read returns zero.
0
CGM
Clock Generation Mode.
0 = No additional ratio is applied to the PLL and faster lock times are possible.
1 = A 25/16 ratio is applied to the PLL allowing for a more flexible choice of MCLK frequencies
while slowing down the PLL lock time.
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