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參數(shù)資料
| 型號： | SI3014-KS |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 28/64頁 |
| 文件大小： | 0K |
| 描述： | IC LINE-SIDE DAA 16SOIC |
| 標(biāo)準(zhǔn)包裝： | 48 |
| 系列： | ISOcap™ |
| 數(shù)據(jù)格式： | 使用 ASK 的家用電源線路 |
| 電源電壓： | 3.3V，5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC N |
| 包裝： | 管件 |
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Si3038
34
Rev. 2.01
Slot 12: Modem GPIO Control
Slot 12 contains latency critical signals for the Si3014
and the GPIO of the Si3024. See Table 22.
Slots 3, 4, 6–9, 11: Not Used
The Si3038 always pads audio output frame slots 3, 4,
6–9, and 11 with 0s.
AC-Link Audio Input Frame (SDATA_IN)
The audio input frame data streams correspond to the
multiplexed bundles of all digital input data targeting the
AC’97 controller. This is the case with the audio output
frame; each AC-link audio input frame consists of 12
20-bit time slots. Slot 0 is a special reserved time slot
containing 16 bits that are used by the AC-link protocol
infrastructure.
Within slot 0, the first bit is a global bit (SDATA_IN slot
0, bit 15) that flags whether the Si3024 is in the Codec
Ready state or not. If the Codec Ready bit is a 0, the
Si3024 is not ready for normal operation. This condition
is normal following the deassertion of reset (e.g., while
the Si3024’s voltage references settle). When the AC-
link Codec Ready indicator bit is a 1, the AC-link and
Si3024 control and status registers are in a fully
operational state. The AC’97 controller must further
probe the Powerdown Control/Status register to
determine exactly which subsections, if any, are ready.
Before any attempts to put the Si3038 chipset into
operation, the AC’97 controller should poll the first bit in
the audio input frame (SDATA_IN slot 0, bit 15) for an
indication that the Si3024 is Codec Ready. When the
Si3024 is sampled Codec Ready, then the next 12 bit
positions sampled by the AC’97 controller indicate
which of the corresponding 12 time slots are assigned
to input data streams, and that they contain valid data.
Figure 31 illustrates the time slot-based AC-link
protocol.
A new audio input frame begins with a low to high
transition of SYNC. SYNC is synchronous to the rising
edge of BIT_CLK. On the next falling edge of BIT_CLK,
the Si3024 samples the assertion of SYNC. This falling
edge marks the time when both sides of AC-link are
aware of the start of a new audio frame.
On the next rising of BIT_CLK, the Si3024 transitions
SDATA_IN into the first bit position of slot 0 (Codec
Table 22. Slot 12
GPIO
Name
Sense
Description
GPIO15
LINE2_GPIO_B
in/out
GPIO pin B, Line 2
GPIO14
LINE2_GPIO_A
in/out
GPIO pin A, Line 2
GPIO13
LINE2_DLCS
in
Delta Loop Current Sense, Line 2
GPIO12
LINE2_CID
out
Caller ID path enable, Line 2
GPIO11
LINE2_RI
in
Ring Detect, Line 2
GPIO10
LINE2_OH
out
Off Hook, Line 2
GPIO9:6
Reserved
GPIO5
LINE1_GPIO_B
in/out
GPIO pin B, Line 1
GPIO4
LINE1_GPIO_A
in/out
GPIO pin A, Line 1
GPIO3
LINE1_DLCS
in
Delta Loop Current Sense, Line 1
GPIO2
LINE1_CID
out
Caller ID path enable, Line 1
GPIO1
LINE1_RI
in
Ring Detect, Line 1
GPIO0
LINE1_OH
out
Off Hook, Line 1
Vendor Optional
Bit 3
Reserved
Bit 2
LINE2_FDT
in
Frame Detect, Line 2
Bit 1
LINE1_FDT
in
Frame Detect, Line 1
Bit 0
GPIO_INT
in
GPIO state change
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參數(shù)描述 |
|---|---|
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| SI3015-BSR | 功能描述:電信線路管理 IC CONTACT SILICON LABS FOR AVAILABILITY RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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