參數(shù)資料
型號: SI3014-KS
廠商: Silicon Laboratories Inc
文件頁數(shù): 1/64頁
文件大小: 0K
描述: IC LINE-SIDE DAA 16SOIC
標(biāo)準(zhǔn)包裝: 48
系列: ISOcap™
數(shù)據(jù)格式: 使用 ASK 的家用電源線路
電源電壓: 3.3V,5V
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC N
包裝: 管件
Rev. 2.01 9/01
Copyright 2001 by Silicon Laboratories
Si3038-DS201
Si3038
GLOBAL MC’97 SILICON DAA
Features
Complete DAA includes:
Applications
Description
The Si3038 is an integrated direct access arrangement (DAA) chipset that
provides a digital, programmable line interface to meet global telephone
line requirements. Available in two 16-pin small outline packages (AC’97
interface on Si3024 and phone-line interface on Si3014), the chipset
eliminates the need for an analog front end (AFE), an isolation
transformer, relays, opto-isolators, and a 2- to 4-wire hybrid. The Si3038
dramatically reduces the number of discrete components and cost
required to achieve compliance with global regulatory requirements. The
Si3024 complies with the AC’97 2.1 specification.
Functional Block Diagram
AC’97 2.1 Compliant
Primary or Secondary Codec
Global Phone Line Interface
Compliant with FCC, CTR21,
JATE, and Other PTTs
84 dB Dynamic Range TX/RX
Paths
3.3 V or 5 V Power Supply
Greater than 3000 V Isolation
Integrated Ring Detector
Wake-Up On Ring
Caller ID Support
Integrated Analog Front End
2- to 4-Wire Hybrid
Low-Power Standby Mode
Low Profile SOIC Packages
Patented ISOcap Technology
Software Modems
Audio/Telephony Sub-Systems
Audio/Modem Riser Cards (AMR)
Mobile Daughter Cards (MDC)
Mini-PCI Cards
Si3024
Clock
Control
Interface
Isolation
Interface
XOUT
MCLK/XIN
BIT_CLK
SYNC
GPIO_A
GPIO_B
RESET
SDATA_IN
AC'97
Digital
Interface
SDATA_OUT
ID0
ID1
Hybrid
and
DC
Termination
Ring Detect
Off-Hook
FILT
FILT2
REF
DCT
VREG2
REXT
REXT2
RNG1
RNG2
QB
QE
QE2
RX
Si3014
Isolation
Interface
VREG
US Patent # 5,870,046
US Patent # 6,061,009
Other Patents Pending
Ordering Information:
Pin Assignments
Si3024 (SOIC)
Si3024 (TSSOP)
Si3014 (SOIC or TSSOP)
116
215
314
413
512
611
710
89
GPIO_A
ID1
V
A
GND
C1A
ID0
AOUT
GPIO_B
MCLK/XIN
XOUT
BIT_CLK
SDA TA _IN
SY NC
SDATA_OUT
RESET
V
D
116
215
314
413
512
611
710
89
V
D
XOUT
MCLK/XIN
GPIO_A
GPIO_B
ID1
V
A
BIT_CLK
SDATA_IN
SDATA_OUT
SY NC
AOUT
C1A
ID0
GND
RESET
116
215
314
413
512
611
710
89
QE2
DCT
IGND
RNG1
QB
RNG2
QE
C1B
FILT2
RX
REXT
REXT2
REF
VREG2
VREG
FILT
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