參數(shù)資料
型號: SI3011-F-FS
廠商: Silicon Laboratories Inc
文件頁數(shù): 29/128頁
文件大小: 0K
描述: IC VOICE DAA GCI/PCM/SPI 16SOIC
標準包裝: 48
系列: ISOcap™
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 16-SOIC N
包裝: 管件
Si3050 + Si3011/18/19
124
Rev. 1.5
Table 37. 20-Pin Quad Flat No-Lead (QFN) PCB Land Pattern Dimensions
Dimension
MIN
MAX
D
2.71 REF
D2
1.60
1.80
e0.50 BSC
E
2.71 REF
E2
1.60
1.80
f2.53 BSC
GD
2.10
GE
2.10
W
0.34
X
0.28
Y
0.61 REF
ZE
3.31
ZD
3.31
Notes:
General
1. All dimensions shown are in milllimeters (mm) unless otherwise noted.
2.
Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3.
This Land Pattern Design is based on IPC-SM-782 guidelines.
4.
All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Solder Mask Design
1. All pads are to be non-solder mask defined (NSMD). Clearance between the solder
mask and the metal pad is to be 60
m minimum, all the way around the pad.
Stencil Design
1.
A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be
used to assure good solder paste release.
2.
The stencil thickness should be 0.125 mm (5 mils).
3.
The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4.
A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides
approximately 70% solder paste coverage on the pad, which is optimum to assure
correct component stand-off.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2.
The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification
for Small Body Components.
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